REV. B
AD7470/AD7472
–7–
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7470
NC = NO CONNECT
DB7 DB6
DB8 DB5
(MSB) DB9 DB4
AV
DD
V
DRIVE
REF IN DV
DD
V
IN
DGND
AGND DB3
CS
DB2
RD
DB1
CONVST
DB0 (LSB)
CLKIN NC
BUSY NC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7472
DB9 DB8
DB10 DB7
(MSB) DB11 DB6
AV
DD
V
DRIVE
REF IN DV
DD
V
IN
DGND
AGND DB5
CS
DB4
RD
DB3
CONVST
DB2
CLKIN DB1
BUSY DB0 (LSB)
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
CS Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The conversion
result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to
the same AND gate on the input so the signals are interchangeable. CS can be hardwired permanently low.
RD Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to same
AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently low, in
which case the data bus is always active and the result of the new conversion is clocked out slightly before to the
BUSY line going low.
CONVST Conversion Start Input. Logic input used to initiate conversion. The input track-and-hold amplifier goes from
track mode to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point.
The conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep
mode, the next rising edge of CONVST wakes up the part. Wake-up time for the part is typically 1 µs.
CLK IN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7472 takes 14 clock cycles, and conversion time for the AD7470 takes 12 clock cycles. The frequency of this
master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is
not converting, the clock-in pad is in three-state and thus no clock is going through the part.
BUSY BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after the
falling edge of CONVST and stays high for the duration of conversion. Once conversion is complete and the con-
version result is in the output register, the BUSY line returns low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low. If the CONVST
input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
REF IN Reference Input. An external reference must be applied to this input. The voltage range for the external reference
is 2.5 V ±1% for specified performance.
AV
DD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/
AD7472. The AV
DD
and DV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V
apart even on a transient basis. This supply should be decoupled to AGND.
DV
DD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7470/
AD7472 aside from the output drivers. The DV
DD
and AV
DD
voltages should ideally be at the same potential and
must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
AGND Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
REV. B
AD7470/AD7472
–8–
PIN FUNCTION DESCRIPTIONS (continued)
Mnemonic Function
DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7470 and AD7472. The
DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even
on a transient basis.
V
IN
Analog Input. Single-ended analog input channel. The input range is 0 V to REF IN. The analog input presents a
high dc input impedance.
V
DRIVE
Supply Voltage for the Output Drivers, 2.7 V to 5.25 V. This voltage determines the output high voltage for the
data output pins. It allows AV
DD
and DV
DD
to operate at 5 V (and maximize the dynamic performance of the
(ADC), while the digital outputs can interface to 3 V logic.
DB0–DB9/11 Data Bit 0 to Data Bit 9 (AD7470) and DB11 (AD7472). Parallel digital outputs that provide the conversion result
for the part. These are three-state outputs that are controlled by CS and RD. The output high voltage level for these
outputs is determined by the V
DRIVE
input.
REV. B
AD7470/AD7472
–9–
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Gain Error
The last transition should occur at the analog value 1.5 LSB
below the nominal full scale. The first transition is a 0.5 LSB
above the low end of the scale (zero in the case of AD7470/
AD7472). The gain error is the deviation of the actual difference
between the first and last code transitions from the ideal differ-
ence between the first and last code transitions with offset errors
removed.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-Hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (f
S
/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit con-
verter is 62 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. For the AD7470/AD7472 it is
defined as
THD dB
VVVVV
V
() log
()
=
++++
20
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5,
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second-order terms include (fa + fb) and (fa – fb), while the
third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7470/AD7472 are tested using the CCIF standard
where two input frequencies near the top end of the input band-
width are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
In a sample-and-hold, the time required after the hold command
for the switch to open fully is the aperture delay. The sample is,
in effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay.
In other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise which modulates the phase
of the hold command. This specification establishes the ulti-
mate timing error, hence the maximum sampling frequency
for a given resolution. This error will increase as the input
dV/dt increases.

AD7472ARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit 2.7V-5.25V 1.5MSPS Lo Pwr
Lifecycle:
New from this manufacturer.
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