LTC2752
14
2752f
writing code or span. If a 32-bit input sequence is used,
the first eight bits must be zeros, followed by the same
sequence as for a 24-bit wide input. Figure 3 shows the
input and readback sequences for both 24-bit and 32-bit
operations.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output.The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. SRO outputs a logic low (when CS/LD
is low) until the readback data begins. For a 24-bit input
sequence, the 16 readback bits are shifted out on the
falling edges of clocks 8-23, suitable for shifting into a
microprocessor on the rising edges of clocks 9-24. For a
32-bit sequence, the bits are shifted out on clocks 16-31;
see Figure 3b.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
The codes for the command word (C3-C0) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-A0).
Readback
In addition to the Input and DAC registers, each DAC has
one Readback register associated with it. When a Read
command is issued to a DAC, the contents of one of its
four buffers (Input and DAC registers for each of Span
operaTion
and Code) is copied into its Readback register and seri-
ally shifted out through the SRO pin. Figure 3 shows the
loading and readback sequences.
In the data field (D15-D0) of any non-read instruction cycle,
SRO shifts out the contents of the buffer that was specified
in the preceding command. This “rolling readback” default
mode of operation can dramatically reduce the number
of instruction cycles needed, since any command can be
verified during succeeding commands with no additional
overhead. See Figure 4. Table 1 shows the storage location
(‘readback pointer’) of the data which will be output from
SRO during the next instruction.
For Read commands, the data is shifted out during the Read
instruction itself (on the 16 falling SCK edges immediately
after the last address bit is shifted in on SDI). When check-
ing the span of a DAC using SRO, the span bits are the last
four bits shifted out, corresponding to their sequence and
positions when writing a span. See Figure 3.
Span Readback in Manual Span Configuration
If a Span DAC register is chosen for readback, SRO re-
sponds by outputting the actual output span; this is true
whether the LTC2752 is configured for SoftSpan (M-SPAN
tied to GND) or manual span (M-SPAN tied to V
DD
) use.
In SoftSpan configuration, SRO outputs the span code
from the Span DAC register (programmed through the
SPI port). In manual span configuration, the active span
is controlled by pins S2, S1 and S0, so SRO outputs the
logic values of these pins. The span code bits S2, S1 and
S0 always appear in the same order and positions in the
SRO output sequence; see Figure 3.
