LTC2752
19
2752f
operaTion
The offset adjust pin V
OSADJX
can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
V LSB
V
V
OS
VOSADJX
RINX
[ ]
=
512
A 5V control voltage applied to V
OSADJX
produces V
OS
=
–512 LSB in any output range, assuming a 5V reference
voltage at R
INX
.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
V
OS
= –(
1
/
128
)V
OSADJX
[0V to 5V, ±2.5V spans]
V
OS
= –(
1
/
64
)V
OSADJX
[0V to 10V, ±5V, –2.5V to
7.5V spans]
V
OS
= –(
1
/
32
)V
OSADJX
[±10V span]
The gain error adjust pins GE
ADJX
can be used to null
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
GE
V
V
GEADJX
RINX
= 512
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V
REFX
. In voltage terms, the V
REFX
delta is inverted and attenuated by a factor of 128.
V
REFX
= –(
1
/
128
)GE
ADJX
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
The V
OSADJX
pins have an input impedance of 1.28MΩ.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling perfor-
mance of the LTC2752. They should be shorted to GND
if not used.
The GE
ADJX
pins have an input impedance of 2.56MΩ, and
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2752, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply V
DD
dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
LTC2752
20
2752f
applicaTions inForMaTion
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC2752, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 4 and 5 contain equations for evaluating the ef-
fects of op amp parameters on the LTC2752’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
Table 6 contains a partial list of Linear Technology preci-
sion op amps recommended for use with the LTC2752.
The easy-to-use design equations simplify the selection
of op amps to meet the system’s specified error budget.
Select the amplifier from Table 6 and insert the specified
op amp parameters in Table 5. Add up all the errors for
each category to determine the effect the op amp has on
the accuracy of the part. Arithmetic summation gives an
(unlikely) worst-case effect. A root-sum-square (RMS)
summation produces a more realistic estimate.
Table 4. Coefficients for the Equations of Table 5
OUTPUT RANGE A1 A2 A3 A4 A5
5V 1.1 2 1 1
10V 2.2 3 0.5 1.5
±5V 2 2 1 1 1.5
±10V 4 4 0.83 1 2.5
±2.5V 1 1 1.4 1 1
–2.5V to 7.5V 1.9 3 0.7 0.5 1.5
A3 • V
OS1
• 19.6 •
I
B1
• 0.13 •
0
A4 • V
OS2
• 13.1 •
A4 • I
B2
• 0.13 •
A4 •
5V
V
REF
5V
V
REF
16.5
A
VOL1
V
OS1
(mV)
I
B1
(nA)
A
VOL1
(V/mV)
V
OS2
(mV)
I
B2
(nA)
A
VOL2
(V/mV)
OP AMP
V
OS1
• 3 •
I
B1
• 0.0003 •
A1 •
0
0
0
INL (LSB)
5V
V
REF
5V
V
REF
1.5
A
VOL1
66
A
VOL2
131
A
VOL1
131
A
VOL1
131
A
VOL2
131
A
VOL2
V
OS1
• 0.78 •
I
B1
• 0.00008 •
A2 •
0
0
0
DNL (LSB)
5V
V
REF
5V
V
REF
A3 • V
OS1
• 13.1 •
I
B1
• 0.13 •
0
0
0
0
UNIPOLAR
OFFSET (LSB)
5V
V
REF
5V
V
REF
5V
V
REF
V
OS1
• 13.1 •
I
B1
• 0.0018 •
A5 •
V
OS2
• 26.2 •
I
B2
• 0.26 •
BIPOLAR GAIN
ERROR (LSB)
5V
V
REF
5V
V
REF
5V
V
REF
5V
V
REF
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
5V
V
REF
5V
V
REF
5V
V
REF
5V
V
REF
5V
V
REF
V
OS1
• 13.1 •
I
B1
• 0.0018 •
A5 •
V
OS2
• 26.2 •
I
B2
• 0.26 •
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2752 with Relevant Specifications
AMPLIFIER
AMPLIFIER SPECIFICATIONS
V
OS
µV
I
B
nA
A
VOL
V/mV
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
t
SETTLING
with LTC2752
µs
POWER
DISSIPATION
mW
LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp
LTC2752
21
2752f
applicaTions inForMaTion
Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on INL and DNL. For
example, for the LTC2752 with a 5V reference in 5V unipolar
mode, a 250µV op amp offset will cause a 3.3LSB zero-
scale error and a 3.3LSB gain error; but only 0.75LSB of
INL degradation and 0.2LSB of DNL degradation.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, con-
sult an op amp’s data sheet to find the worst-case V
OS
and I
B
over temperature. Then, plug these numbers into
the V
OS
and I
B
equations from Table 5 and calculate the
temperature-induced effects.
For applications where fast settling time is important, Ap-
plication Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time, offers a thorough discus-
sion of 16-bit DAC settling time and op amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2752 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2752
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
There are three primary error sources to consider
when selecting a precision voltage reference for 16-bit
applications: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s apparent INL and DNL performance. If a refer-
ence is chosen with a loose output voltage temperature
coefficient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient conditions.
Minimizing the error due to reference temperature coef-
ficient can be achieved by choosing a precision reference
with a low output voltage temperature coefficient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-noise
ratio. Care should be exercised in selecting a voltage refer-
ence with as low an output noise voltage as practical for the
system resolution desired. Precision voltage references,
like the LT1236 and LTC6655, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2752 with Relevant Specifications
REFERENCE
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% Max 5ppm/°C Max 12µV
P-P
LT1236A-5,
LT1236A-10
±0.05% Max 5ppm/°C Max 3µV
P-P
LT1460A-5,
LT1460A-10
±0.075% Max 10ppm/°C Max 20µV
P-P
LT1790A-2.5 ±0.05% Max 10ppm/°C Max 12µV
P-P
LTC6652A-2.048 ±0.05% Max 5ppm/°C Max 2.1ppm
P-P
LTC6652A-2.5 2.1ppm
P-P
LTC6652A-3 2.1ppm
P-P
LTC6652A-3.3 2.2ppm
P-P
LTC6652A-4.096 2.3ppm
P-P
LTC6652A-5 2.8ppm
P-P
LT6655A-25,
LT6655A-5
±0.025% Max 2ppm/°C Max 0.25ppm
P-P

LTC2752ACLX#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual16-Bit Serial SoftSpan IOUT DACs ( 1LSB INL Max)
Lifecycle:
New from this manufacturer.
Delivery:
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