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LTC2752ACLX#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC2752
16
2752f
operaTion
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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23
24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C300000000
CS/LD
SCK
SDI
COMMAND WORD ADDRESS WORD DAC CODE OR DAC SPAN
32-BIT DATA STREAM
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0000000000
SRO
t
2
t
3
t
4
t
1
t
9
D15
17
SCK
SDI
SRO
D14D15
18
D14
8 ZEROS
Hi-Z
Hi-Z
READBACK CODE
2752 F04
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0000000000
SRO
READBACK SPAN
SPAN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
CS/LD
SCK
SDI
SRO
Hi-Z
Hi-Z
COMMAND WORD
READBACK CODE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S00
SRO
READBACK SPAN
ADDRESS WORD DAC CODE OR DAC SPAN
24-BIT DATA STREAM
2752 F03
SPAN
Figure 3a. 24-Bit Instruction Sequence
Figure 3b. 32-Bit Instruction Sequence
LTC2752
17
2752f
operaTion
Table 1. Command Codes
CODE
COMMAND
READBACK POINTER–
CURRENT INPUT WORD W
0
READBACK POINTER–
NEXT INPUT WORD W
+1
C3 C2 C1 C0
0 0 1 0 Write Span DAC n Set by Previous Command Input Span Register DAC n
0 0 1 1 Write Code DAC n Set by Previous Command Input Code Register DAC n
0 1 0 0 Update DAC n Set by Previous Command DAC Span Register DAC n
0 1 0 1 Update All DACs Set by Previous Command DAC Code Register DAC n
0 1 1 0 Write Span DAC n
Update DAC n
Set by Previous Command DAC Span Register DAC n
0 1 1 1 Write Code DAC n
Update DAC n
Set by Previous Command DAC Code Register DAC n
1 0 0 0 Write Span DAC n
Update All DACs
Set by Previous Command DAC Span Register DAC n
1 0 0 1 Write Code DAC n
Update All DACs
Set by Previous Command DAC Code Register DAC n
1 0 1 0 Read Input Span Register DAC n Input Span Register DAC n
1 0 1 1 Read Input Code Register DAC n Input Code Register DAC n
1 1 0 0 Read DAC Span Register DAC n DAC Span Register DAC n
1 1 0 1 Read DAC Code Register DAC n DAC Code Register DAC n
1 1 1 1 No Operation Set by Previous Command DAC Code Register DAC n
– System Clear – DAC Span Register DAC A
– Initial Power-Up or Power Interupt – DAC Span Register DAC A
Codes not shown are reserved–do not use
Table 2. Address Codes
A3 A2 A1 A0 n
0 0 0
×
DAC A
0 0 1
×
DAC B
1 1 1
×
All DACs (Note 1)
Codes not shown are reserved–do not use.
×
= Don’t Care.
Note 1. If readback is taken using the All DACs address, the LTC2752
defaults to DAC A.
Table 3. Span Codes
S3 S2 S1 S0 SPAN
0 0 0 0 Unipolar 0V to 5V
0 0 0 1 Unipolar 0V to 10V
0 0 1 0 Bipolar –5V to 5V
0 0 1 1 Bipolar –10V to 10V
0 1 0 0 Bipolar –2.5V to 2.5V
0 1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use
SDI
SRO
...
WRITE CODE
DAC A
READ
CODE INPUT
REGISTER DAC A
WRITE CODE
DAC B
READ
CODE INPUT
REGISTER DAC B
WRITE SPAN
DAC C
READ
SPAN INPUT
REGISTER DAC A
WRITE SPAN
DAC B
READ
SPAN INPUT
REGISTER DAC B
UPDATE
ALL DACs
READ
CODE DAC
REGISTER DAC A
...
2754 F04
Figure 4. Rolling Readback
LTC2752
18
2752f
a) CS/LD↓ (Note that after power-on, the code in
Input register is zero)
Clock SDI =
0000 0000 0011 0010 1000 0000 0000 0000
b)
CS/LD↑
Code Input register
- Code of DAC B set to
midscale setting.
c)
CS/LD↓
Clock SDI =
0000 0000 0010 0010 0000 0000 0000 0100
Data out on SRO = 1000 0000 0000 0000 V
erifies
that Code Input register- DAC B is at midscale
setting.
d)
CS/LD↑
Span Input register
- Range of DAC B set to
Bipolar ±2.5V range.
e)
CS/LD↓
Clock SDI =
0000 0000 1010 0010 XXXX XXXX XXXX XXXX
Data Out on SRO = 0000 0000 0000 0100
Verifies that Span Input register- range of DAC B
set to Bipolar ±2.5V Range.
CS/LD↑
f)
CS
/LD↓
Clock SDI =
0000 0000 0100 0010 XXXX XXXX XXXX XXXX
g)
CS/LD↑
Update DAC B for both Code and Range
h)
Alternatively steps f and g could be replaced with
LDAC .
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2752, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
operaTion
Examples
1. Using a 24-bit instruction, load DAC A with the unipolar
range of 0V to 10V, output at zero volts and DAC B with
the bipolar range of ±10V, outputs at zero volts. Note all
DAC outputs should change at the same time.
a) CS
/LD↓
Clock SDI = 0010 1111 0000 0000 0000 0011
b)
CS/LD↑
Span Input register
- Range of all DACs set to
bipolar ±10V
.
c)
CS/LD↓
Clock SDI = 0010 0000 0000 0000 0000 0001
d)
CS/LD↑
Span Input register
- Range of DAC A set to
unipolar 0V to 10V
.
e)
CS/LD↓
Clock SDI = 0011 1111 1000 0000 0000 0000
f)
CS/LD↑
Code Input register
- Code of all DACs set to
midscale.
g)
CS/LD↓
Clock SDI = 0011 0000 0000 0000 0000 0000
h)
CS/LD↑
Code Input register
- Code of DAC A set to
zero code.
i)
CS/LD↓
Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX
j)
CS/LD↑
Update all DACs for both Code and Range.
k)
Alternatively steps i and j could be replaced with
LDAC .
2. Using a 32-bit load sequence, load DAC B with bipolar
±2.5V and its output at zero volts. Use readback to check
Input register contents before updating the DAC output
(i.e., before copying Input register contents into DAC
register).
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LTC2752ACLX#PBF

Mfr. #:
Buy LTC2752ACLX#PBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual16-Bit Serial SoftSpan IOUT DACs ( 1LSB INL Max)
Lifecycle:
New from this manufacturer.
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