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SST39LF010-45-4C-B3KE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
16
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
A
Microchip Technology Company
Figure 8: CE# Controlled Program Cycle Timing Diagram
Figure 9: Data# Polling Timing Diagram
1150 F05.0
ADDRESS A
MS-0
DQ
7-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
T
BP
Note: A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040
1150 F06.0
ADDRESS A
MS-0
DQ
7
DD# D# D
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Note: A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
17
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
A
Microchip Technology Company
Figure 10:Toggle Bit Timing Diagram
Figure 11:WE# Controlled Sector-Erase Timing Diagram
1150 F07.0
ADDRESS A
MS-0
DQ
6
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040
1150 F08.0
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 3055AA 80 AA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
SA
X
= Sector Address
A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
18
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
A
Microchip Technology Company
Figure 12:WE# Controlled Chip-Erase Timing Diagram
Figure 13:Software ID Entry and Read
1150 F17.0
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
1150 F09.2
Note: Device ID = D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-byte Sequence for
Software ID Entry
T
WP
T
WPH
T
AA
BF
Device ID
55AA 90
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SST39LF010-45-4C-B3KE

Mfr. #:
Buy SST39LF010-45-4C-B3KE
Manufacturer:
Microchip Technology
Description:
NOR Flash 128K X 8 45ns
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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