SST39LF010-45-4C-B3KE

©2011 Silicon Storage Technology, Inc. DS25023A 08/11

Data Sheet

Microchip Technology Company

Commands are used to initiate the memory operation functions of the device. Commands are written

to the device using standard microprocessor write sequences. A command is written by asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

is the output control and is used to gate data from the output pins. The data bus is in high impedance

state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure

6).

The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis.

Before programming, the sector where the byte exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte load sequence for Software Data Protec-

tion. The second step is to load byte address and byte data. During the Byte-Program operation, the

addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal

WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the

Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any commands written during the internal Pro-

gram operation will be ignored.

(SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse,

while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 11 for timing waveforms. Any commands written during the

Sector-Erase operation will be ignored.

The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which

allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

©2011 Silicon Storage Technology, Inc. DS25023A 08/11

Data Sheet

Microchip Technology Company

The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect

the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time.

The software detection includes two status bits: Data# Polling (DQ

Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or

Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ

. In order to prevent spurious rejection, if an erroneous result occurs, the software

©2011 Silicon Storage Technology, Inc. DS25023A 08/11

Data Sheet

Microchip Technology Company

attempt to read DQ

completed, DQ

following completion of an internal Write operation, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs.

During internal Erase operation, any attempt to read DQ

operation is completed, DQ

During the internal Program or Erase operation, any consecutive attempts to read DQ

Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Tog-

gle Bit timing diagram and Figure 18 for a flowchart.

The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to

protect nonvolatile data from inadvertent writes.

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

V

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-