LTC4264
3
4264f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: Active high PWRGD pin internal clamp circuit self-regulates to 14V
with respect to V
OUT
.
Note 4: The LTC4264 operates with a negative supply voltage in the range of
–1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defi ned to be –57V. See Applications Information.
Note 6: The LTC4264 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specifi ed in the Electrical
Characteristics are with respect to LTC4264 pins and are designed to meet
IEEE 802.3af specifi cations when the drop from the two diodes is included.
See Applications Information.
Note 7: Signature resistance is measured via the two-point ΔV/ΔI method
as defi ned by IEEE 802.3af. The LTC4264 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifi cations. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 8: The LTC4264 includes hysteresis in the UVLO voltages to preclude
any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will
power up from a voltage source with 20Ω series resistance on the fi rst trial.
Note 9: I
IN_CLASS
does not include classifi cation current programmed at
Pin 3. Total supply current in classifi cation mode will be I
IN_CLASS
+ I
CLASS
(see Note 10).
Note 10: I
CLASS
is the measured current fl owing through R
CLASS
. ΔI
CLASS
accuracy is with respect to the ideal current defi ned as I
CLASS
= 1.237/R
CLASS
.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IL_ILIM
I
LIM_EN
Low Level Input Voltage With Respect to V
IN
(Note 13)
●
1V
V
PWRGD_OUT
Active Low Power Good
Output Low Voltage
I
PWRGD
= 1mA, V
IN
= –54V,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D
Referenced to V
IN
●
0.5 V
I
PWRGD_LEAK
Active Low Power Good Leakage V
IN
= 0V, V
PWRGD
= 57V
●
1µA
V
PWRGD_OUT
Active High Power Good
Output Low Voltage
I
PWRGD
= 0.5mA, V
IN
= –52V, V
OUT
= –4V,
PWRGD Referenced to V
OUT
(Note 14)
●
0.35 V
V
PWRGD_VCLAMP
Active High Power Good
Voltage-Limiting Clamp
I
PWRGD
= 2mA, V
OUT
= 0V,
With Respect to V
OUT
(Note 3)
●
12.0 14.0 16.5 V
I
PWRGD_LEAK
Active High Power Good Leakage V
PWRGD
= 11V, with Respect to V
OUT
,
V
OUT
= V
IN
= –54V
●
1µA
R
ON
On Resistance I = 700mA, V
IN
= –54V
Measured from V
IN
to V
OUT
(Note 11)
●
0.5 0.6
0.8
Ω
Ω
I
OUT_LEAK
V
OUT
Leakage V
IN
= –57V, GND = SHDN = V
OUT
= 0V
●
1µA
I
LIMIT_HIGH
Input Current Limit During Normal
Operation
V
IN
= –54V, V
OUT
= –53V, I
LIM_EN
Floating
(Notes 15, 16)
●
700 750 800 mA
I
LIMIT_LOW
Inrush Current Limit V
IN
= –54V, V
OUT
= –53V (Notes 15, 16)
●
250 300 350 mA
I
LIMIT_DISA
Safeguard Current Limit when
I
LIMIT_HIGH
Disabled
V
IN
= –54V, V
OUT
= –52.5V, I
LIM_EN
Tied to V
IN
(Notes 15, 16, 17)
1.20 1.45 1.65 A
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. (Note 4)
t
CLASSRDY
is the time for I
CLASS
to settle to within ±3.5% of ideal. The current
accuracy specifi cation does not include variations in R
CLASS
resistance. The
total classifi cation current for a PD also includes the IC quiescent current
(I
IN_CLASS
). See Applications Information.
Note 11: This parameter is assured by design and wafer level testing.
Note 12: To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN
pin high with respect to V
IN
. See Applications Information.
Note13: I
LIM_EN
pin is pulled high internally and for normal operation should
be left fl oating. To disable high level current limit, tie I
LIM_EN
to V
IN
. See
Applications Information.
Note 14: Active high power good is referenced to V
OUT
and is valid for
GND-V
OUT
≥ 4V. Measured at –52V due to test hardware limitations.
Note 15: The LTC4264 includes a dual current limit. At turn-on, before C1 is
charged, the LTC4264 current level is set to I
LIMIT_LOW
. After C1 is charged
and with I
LIM_EN
fl oating, the LTC4264 switches to I
LIMIT_HIGH
. With I
LIM_EN
pin tied low, the LTC4264 switches to I
LIMIT_DISA
. The LTC4264 stays in
I
LIMIT_HIGH
or I
LIMIT_DISA
until the input voltage drops below the UVLO turn-
off threshold or a thermal overload occurs.
Note 16: The LTC4264 features thermal overload protection. In the event of
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classifi cation load current and present an invalid power good
signal. Once the LTC4264 cools below the overtemperature limit, the
LTC4264 current limit switches to I
LIMIT_LOW
and normal operation resumes.
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
should be avoided as it may impair device reliability.
Note 17: I
LIMIT_DISA
is a safeguard current limit that is activated when the
normal input current limit (I
LIMIT_HIGH
) is defeated using the I
LIM_EN
pin.
Currents at or near I
LIMIT_DISA
will cause signifi cant package heating and may
require a reduced maximum ambient operating temperature in order to avoid
tripping the thermal overload protection. See Applications Information.
