LTC4264
7
4264f
APPLICATIONS INFORMATION
OVERVIEW
Power over Ethernet (PoE) continues to gain popularity as
more products are taking advantage of having DC power
and high speed data available from a single RJ45 connec-
tor. As PoE is becoming established in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard. To solve this problem and expand the application
of PoE, the LTC4264 breaks the power barrier by allowing
custom PoE applications to deliver up to 35W for power-
hungry PoE applications such as dual band and 802.11n
access points, RFID readers and PTZ security cameras.
The LTC4264 is designed to interface with custom Power
Sourcing Equipment (PSE) to deliver higher power levels
to the PD load. Off-the-shelf high power PSEs are available
today from a variety of vendors for use with the LTC4264
to allow quick implementation of a custom system. Alter-
nately, the system vendor can choose to build their own
high power PSE. Linear Technology provides complete
application information for high power PSE solutions
delivering up to 35W for 2-pair systems and as much as
70W when used in 4-pair systems.
One of the basic architectural decisions associated with
a high power PoE system is whether to deliver power
using four conductors (2-pair) or all eight conductors
(4-pair). Each method provides advantages and the
system vendor needs to decide which method best suits
their application.
2-pair power is used today in 802.3af systems (see
Figure 1). One pair of conductors is used to deliver the
current and a second pair is used for the return while two
conductor pairs are not powered. This architecture offers
the simplest implementation method but suffers from
higher cable loss than an equivalent 4-pair system.
4-pair power delivers current to the PD via two conductor
pairs in parallel (Figure 2). This lowers the cable resistance
but raises the issue of current balance between each con-
ductor pair. Differences in resistance of the transformer,
cable and connectors along with differences in diode bridge
forward voltage in the PD can cause an imbalance in the
currents fl owing through each pair. The 4-pair system in
Figure 2 solves this problem by using two independent
DC/DC converters in the PD. Using this architecture solves
the balancing issue and allows the PD to be driven by two
independent PSEs, for example an Endpoint PSE and a
Midspan PSE. Contact Linear Technology applications
support for detailed information on implementing 2-pair
and 4-pair PoE systems.
4264 F01
SMAJ58A
58V
0.1µF
Tx
Rx
Rx
Tx
SMAJ58A
58V
DATA PAIR
DATA PAIR
V
EE
SENSE GATE OUT
V
DD
CMPD3003
10k
1k
0.1µF
100V
0.25
IRLR3410
S1B
SPARE PAIR
SPARE PAIR
1/4
LTC4259A-1
DGND
BYP AGND
DETECT
3.3V
–54V
CAT 5
DF1501S
DF1501S
RJ45
4
5
4
5
1
2
1
2
3
6
3
6
7
8
7
8
RJ45
PSE PD
R
CLASS
V
IN
PWRGD
V
OUT
LTC4264
GND
DC/DC
CONVERTER
5µF
MIN
+
V
OUT
GND
0.47µF
100V
0.1µF
Figure 1. 2-Pair High Power PoE System Diagram
LTC4264
8
4264f
APPLICATIONS INFORMATION
4264 F02
SMAJ58A
0.1µF
Tx1
Rx1
Rx1
Tx1
SMAJ58A
V
EE
SENSE GATE OUT
V
DD
AUTO
CMPD3003
10k
1k
0.1
µF
0.25
IRLR3410
S1B
1/4
LTC4259A
DGND
BYP AGND
DETECT
3.3V
–54V
1
RJ45
RJ45
CAT5
2
1
2
3
6
3
6
PSE
PD
R
CLASS
V
IN
PWRGD
V
OUT
LTC4264
GND
DF1501S
DF1501S
DC/DC
CONVERTER
5µF
MIN
+
+
+
V
OUT
GND
0.47µF
SMAJ58A
0.1µF
Tx2
Rx2
Rx2
Tx2
V
EE
SENSE GATE OUT
CMPD3003
10k
1k
0.25
IRLR3410
S1B
1/4
LTC4259A
DETECT
–54V
4
5
4
5
7
8
7
8
GND
0.47µF
0.1µF
SMAJ58A
R
CLASS
V
IN
PWRGD
V
OUT
LTC4264
GND
DC/DC
CONVERTER
5µF
MIN
0.1µF
AGND
Figure 2. 4-Pair High Power PoE Gigabit Ethernet System Diagram
The LTC4264 is specifi cally designed to implement the
front end of a high power PD for power-hungry PoE ap-
plications that must operate beyond the power limits of
IEEE 802.3af. LTC4264 uses a precision, dual current limit
that keeps inrush below IEEE 803.2af levels to ensure
interoperability with any PSE. After inrush is complete,
the LTC4264 input current limit switches to the I
LIMIT_HIGH
level, using an onboard, 750mA power MOSFET. This al-
lows a PD (supplied by a custom PSE) to deliver power
above the IEEE 802.3af 12.95W maximum, sending up
to 35W to the PD load. The LTC4264 uses established
IEEE 802.3af detection and classifi cation methods to
maintain compliance and includes an extended program-
mable Class 5 range for use in custom PoE applications.
The LTC4264 features both active-high and active-low
power good signaling for simplifi ed interface to any DC/DC
converter. The SHDN pin on the LTC4264 can be used to
provide a seamless interface for external wall adapter or
other auxiliary power options. The I
LIM_EN
pin provides the
option to remove the high current limit, I
LIMIT_HIGH
. The
LTC4264 includes an onboard signature resistor, precision
UVLO, thermal overload protection and is available in a
thermally-enhanced 12-lead 4mm × 3mm DFN package
for superior high current performance.
OPERATION
The LTC4264 high power PD interface controller has sev-
eral modes of operation depending on the applied input
voltage as shown in Figure 3 and summarized in Table 1.
These various modes satisfy the requirements defi ned
in the IEEE 802.3af specifi cation. The input voltage is
applied to the V
IN
pin with reference to the GND pin and
is always negative.
Table 1. LTC4264 Operational Mode as a Function
of Input Voltage
INPUT VOLTAGE LTC4264 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to –10.1V 25k Signature Resistor Detection
–10.3V to –12.4V Classifi cation Load Current Ramps Up from 0% to
100%
–12.5V to UVLO* Classifi cation Load Current Active
UVLO* to –57V Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold –38.9V
Falling input threshold –30.6V
LTC4264
9
4264f
APPLICATIONS INFORMATION
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
IN
DETECTION V2
–10
TIME
–20
–30
V
IN
(V)
–40
–50
–10
TIME
–20
–30
V
OUT
(V)
–40
–50
–10
TIME
–20
–30
PWRGD (V)PWRGD – V
OUT
(V)
–40
–50
20
10
I
CLASS
PD CURRENT
I
LIMIT_HIGH
I
LIMIT_LOW
dV
dt
I
LIMIT_LOW
C1
=
POWER
BAD
POWER
BAD
POWER
BAD
TIME
TIME
POWER
GOOD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
DETECTION I
2
LOAD, I
LOAD
(UP TO I
LIMIT_HIGH
)
4264 F03
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIMIT_LOW
= 300mA, I
LIMIT_HIGH
= 750mA
I
1
=
V1 – 2 DIODE DROPS
25k
I
LOAD
=
V
IN
R
LOAD
I
2
=
V2 – 2 DIODE DROPS
25k
GND
PSE
I
IN
R
LOAD
R
CLASS
V
OUT
C1
GND
R
CLASS
PWRGD
PWRGD
LTC4264
V
OUT
V
IN
Figure 3. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
SERIES DIODES
The IEEE 802.3af-defi ned operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to handle power received in either
polarity. For this reason, it is common to install diode
bridges BR1 and BR2 between the RJ45 connector and
the LTC4264 (Figure 4). The diode bridges introduce an
offset that affects the threshold points for each range of
operation. The LTC4264 meets the IEEE 802.3af-defi ned
operating modes by compensating for the diode drops
in the threshold points. For the signature, classifi cation,
and the UVLO thresholds, the LTC4264 extends two diode
drops below the IEEE 802.3af specifi cations. Note that
the voltage ranges specifi ed in the LTC4264 Electrical
Specifi cations are referenced with respect to the IC pins.
The LTC4264 threshold points support the use of either
traditional or Schottky diode bridges.
DETECTION
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifi es the device at the end of the cable
as a PD. With the PSE voltage in the detection range, the
LTC4264 presents an internal 25k resistor between the GND
and V
IN
pins. This precision, temperature-compensated
resistor provides the proper characteristics to alert the PSE
that a PD is present and requests power to be applied.
The IEEE 802.3af specifi cation requires the PSE to use
a ΔV/ΔI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must
be included in the overall signature resistance of the PD.
The LTC4264 compensates for the two series diodes in
the signature path by offsetting the internal resistance so
that a PD built with the LTC4264 meets the IEEE 802.3af
specifi cation.
In some designs that include an auxiliary power option,
such as an external wall adapter, it is necessary to control
whether or not the PD is detected by a PSE. With the
LTC4264, the 25k signature resistor can be enabled or
disabled with the SHDN pin (Figure 5). Taking the SHDN

LTC4264CDE#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3af High Power PD Interface
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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