LTC4264
19
4264f
APPLICATIONS INFORMATION
R
CLASS
from Table 2. If a unique load current is required,
the value of R
CLASS
can be calculated as:
R
CLASS
= 1.237V/(I
LOAD
– I
IN_CLASS
)
I
IN_CLASS
is the LTC4264 IC supply current during clas-
sifi cation given in the electrical specifi cations. The R
CLASS
resistor must be 1% or better to avoid degrading the overall
accuracy of the classifi cation circuit. Resistor power dissi-
pation will be 100mW maximum and is transient so heating
is typically not a concern. In order to maintain loop stabil-
ity, the layout should minimize capacitance at the R
CLASS
node. The classifi cation circuit can be disabled by fl oating
the R
CLASS
pin. The R
CLASS
pin should not be shorted to
V
IN
as this would force the LTC4264 classifi cation circuit
to attempt to source very large currents. In this case, the
LTC4264 will quickly go into thermal shutdown.
GND
R
S
10k
R10
100k
PWRGD
D9
MMBD4148
Q1
FMMT2222
–54V
4264 F11
TO
PSE
LTC4264
ACTIVE-LOW ENABLE
V
IN
V
OUT
V
+
PD
LOAD
GND
R
S
10k
R9
100k
PWRGD
D9
5.1V
MMBZ5231B
–54V
TO
PSE
LTC4264
ACTIVE-LOW ENABLE
V
IN
V
OUT
PD
LOAD
–54V
TO
PSE
ACTIVE-HIGH ENABLE
PD
LOAD
RUN
SHDN
GND
PWRGD
LTC4264
V
IN
V
OUT
Power Good Interface
The LTC4264 provides complimentary power good signals
to simplify the DC/DC converter interface. Using the power
good signal to delay converter operation until the load
capacitor is fully charged is recommended as this will help
ensure trouble free start up. The active high PWRGD pin
is controlled by an open collector transistor referenced to
V
OUT
while the active low PWRGD pin is controlled by a
high voltage, open-drain MOSFET referenced to V
IN
. The
designer has the option of using either of these signals to
enable the DC/DC converter and example interface circuits
are shown in Figure 11. When using PWRGD, diode D9
and resistor R
S
protects the converter shutdown pin from
excessive reverse voltage.
Figure 11. Power Good Interface Examples
LTC4264
20
4264f
APPLICATIONS INFORMATION
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the GND pin. Alternately, the SHDN pin can be driven
high with respect to V
IN
. Examples of interface circuits
that disable the signature and all LTC4264 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold volt-
age is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the GND pin
could inadvertently pull SHDN high. To ensure trouble-free
operation, use high voltage layout techniques in the vicinity
of SHDN. If unused, connect SHDN directly to V
IN
.
Load Capacitor
The IEEE 802.3af specifi cation requires that the PD maintain
a minimum load capacitance of 5µF. It is permissible to
have a much larger load capacitor and the LTC4264 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. The LTC4264 maintains IEEE 802.3af com-
pliance when the load capacitor is 180µF or less. A larger
capacitor can be employed in a proprietary, close-system
high power application.
If the load capacitor is too large, there can be a prob-
lem with inadvertent power shutdown by the PSE. For
example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it is
necessary to evaluate the load current and capacitance to
ensure that inadvertent shutdown cannot occur.
Refer also to Thermal Protection in this data sheet for
further discussion on load capacitor selection.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed. The PD
application circuits shown in this data sheet present the
required AC impedance necessary to maintain power.
LAYOUT CONSIDERATIONS FOR THE LTC4264
The LTC4264 is relatively immune to layout problems.
Excessive parasitic capacitance on the R
CLASS
pin should
be avoided. Include an electrically isolated heat sink to
which the exposed pad on the bottom of the package can
be soldered. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as –57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like GND and
LTC4264
21
4264f
APPLICATIONS INFORMATION
V
OUT
, to avoid the possibility of leakage shutting down the
LTC4264. If not used, tie SHDN to V
IN
.
The load capacitor connected between GND and V
OUT
of the LTC4264 can store signifi cant energy when fully
charged. The design of a PD must ensure that this en-
ergy is not inadvertently dissipated in the LTC4264. The
polarity-protection diodes prevent an accidental short
on the cable from causing damage. However, if the V
IN
pin is shorted to GND inside the PD while the capacitor
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4264.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4264 is specifi ed to operate with an absolute
maximum voltage of –90V and is designed to tolerate brief
over-voltage events. However, the pins that interface to the
outside world (primarily V
IN
and GND) can routinely see
peak voltages in excess of 10kV. To protect the LTC4264,
it is highly recommended that the SMAJ58A unidirectional
58V transient voltage suppressor be installed between the
diode bridge and the LTC4264 (D3 in Figure 4).
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4264 or support circuitry
other than the RJ-45 port.

LTC4264CDE#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3af High Power PD Interface
Lifecycle:
New from this manufacturer.
Delivery:
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