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AD2S82ALP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
AD2S80A
–9–
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least signifi-
cant byte will be presented on data output DB9 to DB16 (with
the ENABLE input taken to a logic “LO”) regardless of the
state of the BYTE SELECT pin. Note that when the AD2S80A is
used with a resolution less than 16 bits the unused data lines are
pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input
will present the eight most significant data bits on data output
DB1 and DB8. A logic “LO” will present the least significant
byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli-
cate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulse width of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next consecutive pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to
prevent false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
IN4148
IN4148
RIPPLE
CLOCK
5V
5k⍀
BUSY
5V
10k⍀
1k⍀
0V
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO."
2N3904
Figure 2. Diode Transistor Logic Nand Gate
DIRECTION Output
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This corresponds to a change in input rotation
direction but less than 1 LSB.
DIGITAL TIMING
t
4
BUSY
RIPPLE
CLOCK
DATA
DIR
DATA
BYTE
SELECT
DATA
INHIBIT
INHIBIT
ENABLE
V
H
V
L
V
H
V
H
V
L
V
H
V
H
V
L
V
L
V
L
V
H
V
L
V
L
V
Z
V
H
V
H
V
L
t
13
t
12
t
10
t
7
t
6
t
2
t
1
t
3
t
5
t
9
t
11
t
8
PARAMETER T
MIN
T
MAX
CONDITION
t
1
200 600 BUSY WIDTH V
H
–V
H
t
2
10 25 RIPPLE CLOCK V
H
TO BUSY V
H
t
3
470 580 RIPPLE CLOCK V
L
TO NEXT BUSY V
H
t
4
16 45 BUSY V
H
TO DATA V
H
t
5
3 25 BUSY V
H
TO DATA V
L
t
6
70 140 INHIBIT V
H
TO BUSY V
H
t
7
485 625 MIN DIR V
H
TO BUSY V
H
t
8
515 670 MIN DIR V
H
TO BUSY V
H
t
9
– 600 INHIBIT V
L
TO DATA STABLE
t
10
40 110 ENABLE V
L
TO DATA V
H
t
11
35 110 ENABLE V
L
TO DATA V
L
t
12
60 140 BYTE SELECT V
L
TO DATA STABLE
t
13
60 125 BYTE SELECT V
H
TO DATA STABLE
REV. D
AD2S80A
–10–
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The AD2S80A allows the user greater flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1, and the
section “COMPONENT SELECTION” explains how to select
desired maximum tracking rate and bandwidth values. The
following paragraphs explain in greater detail the circuit of the
AD2S80A and the variations in the dynamic performance avail-
able to the user.
Loop Compensation
The AD2S80A (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Additional compensation in the form of a pole/zero pair is
required to stabilize any Type 2 loop to avoid the loop gain
characteristic crossing the 0 dB axis with 180° of additional
phase lag, as shown in Figure 5.
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as the
input and the digital position data as the output.
The AD2S80A does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer (see Application Note).
A block diagram of the AD2S80A is given in Figure 3.
Ratio Multiplier
The ratio multiplier is the input section of the AD2S80A and
compares the signal from the resolver input angle, θ, to the
digital angle, φ, held in the counter. Any difference between
these two angles results in an analog voltage at the AC ERROR
OUTPUT. This circuit function has historically been called
a “Control Transformer” as it was originally performed by an
electromechanical device known by that name.
The AC ERROR signal is given by
A1 sin (θ–φ) sin
ω
t
where ω = 2 π f
REF
f
REF
= reference frequency
A1, the gain of the ratio multiplier stage is 14.5.
So for 2 V rms inputs signals
AC ERROR output in volts/(bit of error)
= 2 × sin
360
n
× A1
where n = bits per rev
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
giving an AC ERROR output
= 178 mV/bit @ 10 bits resolution
= 44.5 mV/bit @ 12 bits
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits
The ratio multiplier will work in exactly the same way whether
the AD2S80A is connected as a tracking converter or as a con-
trol transformer, where data is preset into the counters using the
DATA LOAD pin.
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S80A is a wide-
band demodulator and is capable of aliasing HF noise down to
within the loop bandwidth. This is most likely to happen where
the resolver is situated in particularly noisy environments, and
the user is advised to fit a simple HF filter R1, C2 prior to the
phase sensitive demodulator.
The attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested filter (R1, C1, R2, C2) is
shown in Figure 1 and gives an attenuation at the reference
frequency (f
REF
) of 3 times at the input to the phase sensitive
demodulator .
Values of components used in the filter must be chosen to ensure
that the phase shift at f
REF
is within the allowable signal to
reference phase shift of the converter.
Phase Sensitive Demodulator
The phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULATOR OUTPUT
pin of
±22
π
×(DEMODULATOR INPUT rms voltage )
PHASE
SENSITIVE
DEMODULATOR
A
1
sin (␪ –
␾
) sin ␻t
AC ERROR
sin ␪ sin ␻t
cos ␪ sin ␻t
DIGITAL
␾
VCO
R5
R6
C5
C4
R4
INTEGRATOR
VELOCITY
CLOCK
DIRECTION
RATIO
MULTIPLIER
Figure 3. Functional Diagram
REV. D
AD2S80A
–11–
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR OUTPUT voltage
will equal the DEMODULATOR INPUT). This provides a
signal at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
DC Error Scaling = 160 mV/bit (10 bits resolution)
= 40 mV/bit (12 bits resolution)
= 10 mV/bit (14 bits resolution)
= 2.5 mV/bit (16 bits resolution)
When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
Integrator
The integrator components (R4, C4, R5, C5) are external to the
AD2S80A to allow the user to determine the optimum dynamic
characteristics for any given application. The section “COMPO-
NENT SELECTION” explains how to select components for a
chosen bandwidth.
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle) and
can be scaled by selection of R6, the VCO input resistor. This is
explained in the section “VOLTAGE CONTROLLED OSCIL-
LATOR (VCO)” below.
To prevent the converter from “flickering” (i.e., continually
toggling by ±1 bit when the quantized digital angle, φ, is not an
exact representation of the input angle, θ) feedback is internally
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to 1 LSB. In order to ensure that this feedback “hys-
teresis” is set to 1 LSB the input current to the integrator must
be scaled to be 100 nA/bit. Therefore,
R4 =
DC Error Scaling (mV /bit )
100 (nA /bit )
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be added
for each 100 nA of input bias current. The method of adjusting out
this offset is given in the section “COMPONENT SELECTION.”
Voltage Controlled Oscillator
(VCO)
The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
During the reset period the input continues to be integrated, the
reset period is constant at 400 ns.
The VCO rate is fixed for a given input current by the VCO
scaling factor:
= 7.9 kHz/µA
The tracking rate in rps per µA of VCO input current can be
found by dividing the VCO scaling factor by the number of LSB
changes per rev (i.e., 4096 for 12-bit resolution).
The input resistor R6 determines the scaling between the con-
verter velocity signal voltage at the INTEGRATOR OUTPUT
pin and the VCO input current. Thus to achieve a 5 V output at
100 rps (6000 rpm) and 12-bit resolution the VCO input cur-
rent must be:
(100 × 4096)/(7900) = 51.8 µA
Thus, R6 would be set to: 5/(51.8 × 10
–6
) = 96 kΩ
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by
Velocity Offset Voltage = R6 × (VCO bias current)
The temperature coefficient of this offset is given by
Velocity Offset Tempco = R6 × (VCO bias current tempco)
where the VCO bias current tempco is typically –1.22 nA/°C.
The maximum recommended rate for the VCO is 1.1 MHz
which sets the maximum possible tracking rate.
Since the minimum voltage swing available at the integrator
output is ±8 V, this implies that the minimum value for R6 is
57 kΩ. As
Max Current A
MinValue R k
=
×
×
=
=
×
=Ω
11 10
79 10
139
6
8
139 10
57
6
3
6
.
.
–
µ
Transfer Function
By selecting components using the method outlined in the sec-
tion “Component Selection,” the converter will have a critically
damped time response and maximum phase margin. The
Closed-Loop Transfer Function is given by:
θ
OUT
θ
IN
=
14 (1+ s
N
)
(s
N
+2.4)(s
N
2
+ 3.4 s
N
+5.8)
where, s
N
, the normalized frequency variable is:
s
N
=
2
π
s
f
BW
and f
BW
is the closed-loop 3 dB bandwidth (selected by the
choice of external components).
The acceleration K
A
, is given approximately by
K
A
= 6 × ( f
BW
)
2
sec
–2
The normalized gain and phase diagrams are given in Figures 4
and 5.
REV. D
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

AD2S82ALP

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Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
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