AD2S80A
–12–
180
180
PHASE PLOT
f
BW
90
135
0.04f
BW
0.02f
BW
0
45
45
90
135
0.4f
BW
0.2f
BW
0.1f
BW
FREQUENCY
2f
BW
Figure 5. AD2S80A Phase Plot
OUTPUT
POSITION
TIME
t
2
t
1
Figure 6. AD2S80A Small Step Response
The small signal step response is shown in Figure 6. The time
from the step to the first peak is t
1
and the t
2
is the time from
the step until the converter is settled to 1 LSB. The times t
1
and
t
2
are given approximately by
t
1
=
1
f
BW
t
2
=
5
f
BW
×
R
12
where R = resolution, i.e., 10, 12, 14, or 16.
The large signal step response (for steps greater than 5 degrees)
applies when the error voltage exceeds the linear range of the
converter.
Typically the converter will take 3 times longer to reach the first
peak for a 179 degrees step.
In response to a velocity step, the velocity output will exhibit the
same time response characteristics as outlined above for the
position output.
ACCELERATION ERROR
A tracking converter employing a Type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant K
A
of the converter.
K
A
=
Input Acceleration
Error in Output Angle
The numerator and denominator must have consistent angular
units. For example if K
A
is in sec
2
, then the input acceleration
may be specified in degrees/sec
2
and the error output in degrees.
Angular measurement may also be specified using radians, min-
utes of arc, LSBs, etc.
K
A
does not define maximum input acceleration, only the error due
to its acceleration. The maximum acceleration allowable before
the converter loses track is dependent on the angular accuracy
requirements of the system.
Angular Accuracy × K
A
= Degrees/sec
2
K
A
can be used to predict the output position error for a
given input acceleration. For example for an acceleration of
100 revs/sec
2
, K
A
= 2.7 × 10
6
sec
2
and 12-bit resolution.
Error in LSBs =
Input acceleration [LSB/sec
2
]
K
A
[sec
2
]
=
100[rev/sec
2
] × 2
12
2.7 ×10
6
= 0.15 LSBs or 47.5 seconds of arc
To determine the value of K
A
based on the passive components
used to define the dynamics of the converter the following
should be used.
K
A
=
4.04 ×10
11
2
n
R6 R4 (C4 +C5)
Where n = resolution of the converter.
R4, R6 in ohms
C5, C4 in farads
12
12
6
9
0.04f
BW
0.02f
BW
0
3
3
6
9
0.4f
BW
0.2f
BW
0.1f
BW
FREQUENCY
GAIN PLOT
2f
BW
f
BW
Figure 4. AD2S80A Gain Plot
REV. D
AD2S80A
–13–
VELOCITY ERRORS
The signal at the INTEGRATOR OUTPUT pin relative to the
ANALOG GROUND pin is an analog voltage proportional to
the rate of change of the input angle. This signal can be used to
stabilize servo loops or in the place of a velocity transducer.
Although the conversion loop of the AD2S80A includes a digital
section there is an additional analog feedback loop around the
velocity signal. This ensures against flicker in the digital posi-
tional output in both dynamic and static states.
A better quality velocity signal will be achieved if the following
points are considered:
1. Protection.
The velocity signal should be buffered before use.
2. Reversion error.
1
The reversion error can be nulled by varying one supply rail
relative to the other.
3. Ripple and Noise.
Noise on the input signals to the converter is the major cause of
noise on the velocity signal. This can be reduced to a minimum
if the following precautions are taken:
The resolver is connected to the converter using separate
twisted pair cable for the sine, cosine and reference signals.
Care is taken to reduce the external noise wherever possible.
An HF filter is fltted before the Phase Sensitive Demodulator
(as described in the section HF FILTER).
A resolver is chosen that has low residual voltage, i.e., a small
signal in quadrature with the reference.
Components are selected to operate the AD2S80A with the
lowest acceptable bandwidth.
Feedthrough of the reference frequency should be removed by
a filter on the velocity signal.
Maintenance of the input signal voltages at 2 V rms will
prevent LSB flicker at the positional output. The analog
feedback or hysteresis employed around the VCO and the
intergrator is a function of the input signal levels (see sec-
tion INTEGRATOR) .
Following the preceding precautions will allow the user to use
the velocity signal in very noisy environments, for example,
PWM motor drive applications. Resolver/converter error curves
may exhibit apparent acceleration/deceleration at a constant
velocity. This results in ripple on the velocity signal of frequency
twice the input rotation.
1
Reversion error, or side-to-side nonlinearity, is a result of differences in the
up and down rates of the VCO.
SOURCES OF ERRORS
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. This error will typically be 1 arc
minute over the operating temperature range.
A description of how to adjust from zero offset is given in the
section COMPONENT SELECTION and the circuit required
is shown in Figure 1.
Differential Phase Shift
Phase shift between the sine and cosine signals from the resolver
is known as differential phase shift and can cause static error.
Some differential phase shift will be present on all resolvers as a
result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional phase
shift can be introduced if the sine channel wires and the cosine
channel wires are treated differently. For instance, different cable
lengths or different loads could cause differential phase shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a
×
b arc minutes
where a = differential phase shift (degrees).
b = signal to reference phase shift (degrees).
This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
section CONNECTING THE RESOLVER). By taking these
precautions the extra error can be made insignificant.
Under static operating conditions phase shift between the refer-
ence and the signal lines alone will not theoretically affect the
converters static accuracy.
However, most resolvers exhibit a phase shift between the signal
and the reference. This phase shift will give rise under dynamic
conditions to an additional error defined by:
Shaft Speed (rps) × Phase Shift (Degrees )
Reference Frequency
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will
exhibit an additional error of:
22 × 20
5000
0.088 Degrees
This effect can be eliminated by placing a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see section CONNECTING THE RESOLVER).
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
REV. D
AD2S80A
–14–
OSCILLATOR
(e.g., OSC1758)
C3
R3
TWISTED PAIR SCREENED CABLE
RESOLVER
S2
S4
S3
S1
R1
R2
1
2
3
4
5
6
7
31
AD2S80A
REF I/P
COS I/P
ANALOG
GND
DIGITAL
GND
SIGNAL
GND
SIN I/P
POWER RETURN
Figure 7. Connecting the AD2S80A to a Resolver
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 7.
In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily
achieved by varying the value of the resistor R2 of the HF filter
(see Figure 1).
Assuming that R1 = R2 = R and C1 = C2 = C
and Reference Frequency =
1
2 π RC
by altering the value of R2, the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
Increasing R2 by 10% introduces a phase lag of 2 degrees.
Decreasing R2 by 10% introduces a phase lead of 2 degrees.
C
R
PHASE LEAD = ARC TAN
1
2fRC
R
C
PHASE LAG = ARC TAN 2fRC
Phase Shift Circuits
TYPICAL CIRCUIT CONFIGURATION
Figure 8 shows a typical circuit configuration for the AD2S80A
in a 12-bit resolution mode. Values of the external components
have been chosen for a reference frequency of 5 kHz and a
maximum tracking rate of 260 rps with a bandwidth of 520 Hz.
Placing the values for R4, R6, C4 and C5 in the equation for K
A
gives a value of 1.67 × 10
6
. The resistors are 0.125 W, 5% toler-
ance preferred values. The capacitors are 100 V ceramic, 10%
tolerance components.
For signal and reference voltages greater than 2 V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal line
and ground and the cosine signal line and ground are the same.
Any difference will result in an additional position error.
For more information on resistive scaling of SIN, COS and
REFERENCE converter inputs refer to the application note,
Circuit Applications of the 2S81 and 2S81 Resolver-to-Digital
Converters.
RELIABILITY
The AD2S80A Mean Time Between Failures (MTBF) has been
calculated according to MIL-HDBK-217E, Figure 10 shows the
MTBF in hours in naval sheltered conditions for AD2S80A/
883B only.
REV. D

AD2S82ALP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
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