Parameter Conditions Min Typ Max Unit
DATA LOAD
Sense Internally Pulled High (100 k) 150 300 ns
to V
S
. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
BUSY
3
Sense Logic HI When Position O/P
Changing
Width 200 600 ns
Load Use Additional Pull-Up 1 LSTTL
DIRECTION
3
Sense Logic HI Counting Up
Logic LO Counting Down
Max Load 3 LSTTL
RIPPLE CLOCK
3
Sense Logic HI
All 1s to All 0s
All 0s to All 1s
Width Dependent on Input Velocity 300
Reset Before Next Busy
Load 3 LSTTL
DIGITAL INPUTS
High Voltage, V
IH
INHIBIT, ENABLE 2.0 V
DB1–DB16, Byte Select
±V
S
= ±10.8 V, V
L
= 5.0 V
Low Voltage, V
IL
INHIBIT, ENABLE 0.8 V
DB1–DB16, Byte Select
±V
S
= ±13.2 V, V
L
= 5.0 V
DIGITAL INPUTS
High Current, I
IH
INHIBIT, ENABLE 100 µA
DB1–DB16
±V
S
= ±13.2 V , V
L
= 5.5 V
Low Current, I
IL
INHIBIT, ENABLE 100 µA
DB1–DB16, Byte Select
±V
S
= ±13.2 V, V
L
= 5.5 V
DIGITAL INPUTS
Low Voltage, V
IL
ENABLE = HI 1.0 V
SC1, SC2, Data Load
±V
S
= ±12.0 V, V
L
= 5.0 V
Low Current, I
IL
ENABLE = HI –400 µA
SC1, SC2, Data Load
±V
S
= ±12.0 V, V
L
= 5.0 V
DIGITAL OUTPUTS
High Voltage, V
OH
DB1–DB16 2.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 4.5 V
I
OH
= 100 µA
Low Voltage, V
OL
DB1–DB16 0.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 5.5 V
I
OL
= 1.2 mA
THREE-STATE LEAKAGE DB1–DB16 Only
Current I
L
±V
S
= ±12.0 V, V
L
= 5.5 V ±100 µA
V
OL
= 0 V
±V
S
= ±12.0 V, V
L
= 5.5 V ±100 µA
V
OH
= 5.0 V
NOTES
1
Refer to small signal bandwidth.
2
Output offset dependent on value for R6.
3
Refer to timing diagram.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
AD2S80A
–3–
REV. D
AD2S80A–SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
RATIO MULTIPLIER
AC Error Output Scaling 10 Bit 177.6 mV/Bit
12 Bit 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit
PHASE SENSITIVE DETECTOR
Output Offset Voltage 12 mV
Gain
In Phase w.r.t. REF –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF ±0.02 V rms/V dc
Input Bias Current 60 150 nA
Input Impedance 1 M
Input Voltage ±8V
INTEGRATOR
Open-Loop Gain At 10 kHz 57 63 dB
Dead Zone Current (Hysteresis) 100 nA/LSB
Input Offset Voltage 15 mV
Input Bias Current 60 150 nA
Output Voltage Range ±V
S
= ±10.8 V dc ±7V
VCO
Maximum Rate ±V
S
= ±12 V dc 1.1 MHz
VCO Rate Positive Direction 7.1 7.9 8.7 kHz/µA
Negative Direction 7.1 7.9 8.7 kHz/µA
VCO Power Supply Sensitivity
Increase +V
S
+0.5 %/V
–V
S
–8.0 %/V
Decrease +V
S
–8.0 %/V
–V
S
+2.0 %/V
Input Offset Voltage 15 mV
Input Bias Current 70 380 nA
Input Bias Current Tempco –1.22 nA/°C
Input Voltage Range ±8V
Linearity of Absolute Rate
Full Range <2 % FSD
Over 0% to 50% of Full Range <1 % FSD
Reversion Error 1.5 % FSD
Sensitivity of Reversion Error ±8 %/V of
to Symmetry of Power Supplies Asymmetry
POWER SUPPLIES
Voltage Levels
+V
S
+10.8 +13.2 V
–V
S
–10.8 –13.2 V
+V
L
+5 +13.2 V
Current
±I
S
±V
S
@ ±12 V 12 23 mA
±I
S
±V
S
@ 13.2 V 19 30 mA
±I
L
+V
L
@ ±5.0 V 0.5 1.5 mA
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
(typical at 25
C unless otherwise noted)
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD2S80A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. D
AD2S80A
–5–
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (+V
S
, –V
S
) . . . . . . . . . ±12 V dc ± 10%
Power Supply Voltage V
L
. . . . . . . . . . . . . . . . . . . 5 V dc ± 10%
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10%
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . . 10% (max)
Phase Shift Between Signal and Reference . . . ±10 Degrees (max)
Ambient Operating Temperature Range
Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C
ABSOLUTE MAXIMUM RATINGS
l
(
with respect to GND
)
+V
S
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc
+V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +V
L
dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –V
S
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW
Operating Temperature
Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C
θ
JC
3
(40-Lead DIP 883 Parts Only) . . . . . . . . . . . . . . . 11°C/W
θ
JC
3
(44-Terminal LCC 883 Parts Only) . . . . . . . . . . . 10°C/W
Storage Temperature (All Grades) . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
CAUTION NOTES:
1
Absolute Maximum Ratings are those values beyond which damage to the device
may occur.
2
Correct polarity voltages must be maintained on the +V
S
and –V
S
pins.
3
With reference to Appendix C of MIL-M-38510.
Bit Weight Table
Binary Resolution Degrees Minutes Seconds
Bits (N) (2
N
) /Bit /Bit /Bit
0 1 360.0 21600.0 1296000.0
1 2 180.0 10800.0 648000.0
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0
4 16 22.5 1350.0 81000.0
5 32 11.25 675.0 40500.0
6 64 5.625 337.5 20250.0
7 128 2.8125 168.75 10125.0
8 256 1.40625 84.375 5062.5
9 512 0.703125 42.1875 2531.25
10 1024 0.3515625 21.09375 1265.625
11 2048 0.1757813 10.546875 632.8125
12 4096 0.0878906 5.273438 316.40625
13 8192 0.0439453 2.636719 158.20313
14 116384 0.0219727 1.318359 79.10156
15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539
17 131072 0.0027466 0.164795 9.88770
18 262144 0.0013733 0.082397 4.94385
PIN CONFIGURATIONS
PIN DESIGNATIONS
MNEMONIC DESCRIPTION
REFERENCE I/P REFERENCE SIGNAL INPUT
DEMOD I/P DEMODULATOR INPUT
AC ERROR O/P RATIO MULTIPLIER OUTPUT
COS COSINE INPUT
ANALOG GROUND POWER GROUND
SIGNAL GROUND RESOLVER SIGNAL GROUND
SIN SINE INPUT
+V
S
POSITIVE POWER SUPPLY
DB1–DB16 PARALLEL OUTPUT DATA
V
L
LOGIC POWER SUPPLY
ENABLE LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE
STATE, LOGIC LO PRESENTS DATA TO THE
OUTPUT LATCHES
BYTE SELECT LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1–DB8
LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1–DB8
INHIBIT LOGIC LO INHIBITS DATA TRANSFER TO
OUTPUT LATCHES
DIGITAL GROUND DlGITAL GROUND
SC1–SC2 SELECT CONVERTER RESOLUTION
DATA LOAD LOGIC LO DB1–DB16 INPUTS LOGIC Hl DB1–D16
OUTPUTS
BUSY CONVERTER BUSY, DATA NOT VALID WHILE
BUSY Hl
DIRECTION LOGIC STATE DEFINES DIRECTION
OF INPUT SIGNAL ROTATION
RIPPLE CLOCK POSITIVE PULSE WHEN CONVERTER OUTPUT
CHANGES FROM 1S TO ALL 0S OR VICE VERSA
–V
S
NEGATIVE POWER SUPPLY
VCO I/P VCO INPUT
INTEGRATOR I/P INTEGRATOR INPUT
INTEGRATOR O/P INTEGRATOR OUTPUT
DEMOD O/P DEMODULATOR OUTPUT
DIP (D) Package
NC = NO CONNECT
SIN
+V
S
DB2
NC
MSB DB1
V
S
RIPPLE CLOCK
DATA LOAD
DIRECTION
BUSY
SC2
NC
DIGITAL GND
SC1
NC
INHIBIT
DB4
DB3
DB6
DB5
DB8
DB7
3124444342414056
7
10
8
9
11
13
12
14
15
17
16
18 19 242320 2221 28272625
33
34
35
36
37
38
39
29
30
31
32
TOP VIEW
(Not to Scale)
AD2S80A
DB9
DB10
DB13
DB11
DB12
DB15
DB14
V
L
LSB DB16
BYTE SELECT
SIGNAL GND
ANALOG GND
DEMOD I/P
COS
AC ERROR O/P
DEMOD O/P
REFERENCE I/P
INTEGRATOR I/P
INTEGRATOR O/P
VCO I/P
NC
ENABLE
LCC (E) Package
DB3
RIPPLE CLK
INHIBIT
ENABLE
DEMOD O/P
INTEGRATOR O/P
V
S
SC1
DIRECTION
INTEGRATOR I/P
VCO I/P
BUSY
DATA LOAD
SC2
DIGITAL GND
BYTE SELECT
V
L
DB16 LSB
DB14
DB15
DB13
DB5
DB7
REFERENCE I/P
DEMOD I/P
ANALOG GND
SIGNAL GND
SIN
AC ERROR O/P
COS
+V
S
MSB DB1
DB2
DB4
DB6
DB8
DB9
DB11
DB10
DB12
13
30
1
2
40
39
5
6
7
36
35
34
3
4
38
37
833
932
10 31
11
12 29
28
14
27
15
26
16
25
17
24
18 23
19
22
20
21
TOP VIEW
(Not to Scale)
AD2S80A
REV. D

AD2S82ALP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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