AD2S80A
–6–
CONNECTING THE CONVERTER
The power supply voltages connected to +V
S
and –V
S
pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to V
L
can be 5 V dc to +V
S
.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +V
S
, –V
S
and ANALOG
GROUND adjacent to the converter. Recommended values
are 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of
100 nF and 10 µF should be connected between +V
L
and
DIGITAL GROUND adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 7 and described in section “CONNECTING
THE RESOLVER.”
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally.
The external components required should be connected as
shown in Figure 1.
CONVERTER RESOLUTION
Two major areas of the AD2S80A specification can be selected
by the user to optimize the total system performance. The reso-
lution of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14, or 16 bits; and the dynamic
characteristics of bandwidth and tracking rate are selected by the
choice of external components.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respectively
(see section COMPONENT SELECTION). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when Data is not changing.
A1
A2
SEGMENT
SWITCHING
R-2R DAC
A3
OUTPUT DATA LATCH
PHASE
SENSITIVE
DETECTOR
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
O/P
AD2S80A
C2
HF FILTER
R1
C1
C3
R3
VCO + DATA
TRANSFER LOGIC
R4
INTEGRATOR
I/P
R9
R8
12V+12V
OFFSET ADJUST
C4
C5
R5
AC ERROR O/P
REFERENCE
I/P
BANDWIDTH
SELECTION
R6
R7
C6
TRACKING
RATE
SELECTION
VELOCITY
SIGNAL
VCO
I/P
SC1 SC2DATA
LOAD
16-BIT UP/DOWN COUNTER
ENABLE
16 DATA BITS
BYTE
SELECT
5V
DIG
GND
BUSY DIRN
INHIBIT
SIN
SIG GND
COS
GND
RIPPLE
CLK
+12V
12V
R2
Figure 1. AD2S80A Connection Diagram
REV. D
AD2S80A
–7–
CONVERTER OPERATION
When connected in a circuit such as shown in Figure 1 the
AD2S80A operates as a tracking resolver-to-digital converter
and forms a Type 2 closed-loop system. The output will auto-
matically follow the input for speeds up to the selected maximum
tracking rate. No convert command is necessary as the conversion
is automatically initiated by each LSB increment, or decre-
ment, of the input. Each LSB change of the converter initiates a
BUSY pulse.
The AD2S80A is remarkably tolerant of input amplitude and
frequency variation because the conversion depends only on the
ratio of the input signals. Consequently there is no need for
accurate, stable oscillator to produce the reference signal. The
inclusion of the phase sensitive detector in the conversion loop
ensures a high immunity to signals that are not coherent or are
in quadrature with the reference signal.
SIGNAL CONDITIONING
The amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic response
will also change, since the dynamic characteristics are propor-
tional to the signal level.
The AD2S80A will not be damaged if the signal inputs are applied
to the converter without the power supplies and/or the reference.
REFERENCE INPUT
The amplitude of the reference signal applied to the converter’s
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.
The AD2S80A will not be damaged if the reference is sup-
plied to the converter without the power supplies and/or the
signal inputs.
HARMONIC DISTORTION
The amount of harmonic distortion allowable on the signal and
reference lines is 10%.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak.) Triangular and sawtooth
waveforms should have a amplitude of 2 V rms.
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
POSITION OUTPUT
The resolver shaft position is represented at the converter output
by a natural binary parallel digital word. As the digital position
output of the converter passes through the major carries, i.e., all
“1s” to all “0s” or the converse, a RIPPLE CLOCK (RC) logic
output is initiated indicating that a revolution or a pitch of the
input has been completed.
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changing state (1 LSB min change) with a corresponding
change in direction.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT. The static
positional accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effects of
offset signals at the INTEGRATOR INPUT (which can be
trimmed out—see Figure 1), and with the following conditions:
input signal amplitudes are within 10% of the nominal; phase
shift between signal and reference is less than 10 degrees.
These operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S80A can be used well
outside these operating conditions providing the above points
are observed.
VELOCITY SIGNAL
The tracking converter technique generates an internal signal at
the output of the integrator (the INTEGRATOR OUTPUT
pin) that is proportional to the rate of change of the input angle.
This is a dc analog output referred to as the VELOCITY signal.
In many applications it is possible to use the velocity signal of
the AD2S80A to replace a conventional tachogenerator.
DC ERROR SIGNAL
The signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by
the tracking loop and is, therefore, proportional to the error
between the input angle and the output digital angle. This is the
dc error of the converter; and as the converter is a Type 2 servo
loop, it will increase if the output fails to track the input for any
reason. It is an indication that the input has exceeded the maxi-
mum tracking rate of the converter or, due to some internal
malfunction, the converter is unable to reach a null. By connect-
ing two external comparators, this voltage can be used as a
“built-in-test.”
REV. D
AD2S80A
–8–
COMPONENT SELECTION
The following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value” component should be used, and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.
PG compatible software is available to help users select the optimum
component values for the AD2S80A, and display the transfer gain,
phase and small step response.
For more detailed information and explanation, see section “CIR-
CUIT FUNCTIONS AND DYNAMIC PERFORMANCE.”
1. HF Filter (R1, R2, C1, C2)
The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs to
the AD2S80A, reaching the Phase Sensitive Detector and
affecting the outputs. R1 and C2 may be omitted—in which
case R2 = R3 and C1 = C3, calculated below—but their use
is particularly recommended if noise from switch mode power
supplies and brushless motor drive is present.
Values should be chosen so that
and f
REF
= Reference frequency (Hz)
This filter gives an attenuation of three times at the input to
the phase sensitive detector.
2. Gain Scaling Resistor (R4)
If R1, C2 are used:
R4 =
E
DC
100 ×10
9
×
1
3
where 100 × 10
9
= current/LSB
If R1, C2 are not used:
R4 =
E
DC
100 × 10
9
where E
DC
= 160 × 10
3
for 10 bits resolution
= 40 × 10
3
for 12 bits
= 10 × 10
3
for 14 bits
= 2.5 × 10
3
for 16 bits
= Scaling of the DC ERROR in volts
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
R3 = 100 k
C 3 >
1
R3 × f
REF
F
with R3 in .
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, T, in revolutions
per second. Note that T must not exceed the maximum
tracking rate or 1/16 of the reference frequency.
R6 =
6. 32 ×10
10
T × n
where n = bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the closed-loop bandwidth (f
BW
) required
ensuring that the ratio of reference frequency to band-
width does not exceed the following guidelines:
Resolution Ratio of Reference Frequency/Bandwidth
10 2.5 : 1
12 4 : 1
14 6 : 1
16 7.5 : 1
Typical values may be 100 Hz for a 400 Hz reference frequency
and 500 Hz to 1000 Hz for a 5 kHz reference frequency.
b. Select C4 so that
C4 =
21
R6 × f
BW
2
F
with R6 in and f
BW
, in Hz selected above.
c. C5 is given by
C5 = 5 × C4
d. R5 is given by
R5 =
4
2 ×π× f
BW
× C5
6. VCO Phase Compensation
The following values of C6 and R7 should be fitted.
C6 = 470 pF, R7 = 68
7. Offset Adjust
Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7 M, R9 = 1 M potentiometer
To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the COS
pin to the REFERENCE INPUT and the SIN pin to the
SIGNAL GROUND and with the power and reference
applied, adjust the potentiometer to give all 0s on the
digital output bits.
The potentiometer may be replaced with select on test resistors
if preferred.
CC k RR k
CC
Rf
REF
1215 1256
12
1
21
== =≤
==
π
REV. D

AD2S82ALP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
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