3
LTC3733/LTC3733-1
3733f
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= V
RUN
= V
SS
= 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
LOADREG
Output Voltage Load Regulation (Note 3)
Measured in Servo Loop, ∆I
TH
Voltage = 1.2V to 0.7V ● 0.1 0.5 %
Measured in Servo Loop, ∆I
TH
Voltage = 1.2V to 2V ● –0.1 –0.5 %
V
REFLNREG
Output Voltage Line Regulation V
CC
= 4.5V to 7V 0.03 %/V
g
m
Transconductance Amplifier g
m
I
TH
= 1.2V, Sink/Source 25µA (Note 3) 2.5 3.05 3.6 mmho
g
mOL
Transconductance Amplifier GBW I
TH
= 1.2V, (g
m
• Z
L
, Z
L
= Series 1k-100kΩ-1nF) 1.5 MHz
V
FCB
Forced Continuous Threshold ● 0.58 0.60 0.62 V
I
FCB
FCB Bias Current V
FCB
= 0.65V 0.2 0.7 µA
V
BINHIBIT
Burst Inhibit Threshold Measured at FCB pin V
CC
– 1.5 V
CC
– 0.7 V
CC
– 0.3 V
UVR Undervoltage SS Reset V
CC
Lowered Until the SS Pin is Pulled Low 3.3 3.8 4.5 V
I
Q
Input DC Supply Current (Note 4)
Normal Mode V
CC
= 5V 2.5 mA
Shutdown V
RUN
= 0V, VID0 to VID4 Open 20 100 µA
V
RUN
RUN Pin ON Threshold V
RUN
, Ramping Positive 1 1.5 1.9 V
I
SS
Soft-Start Charge Current V
SS
= 1.9V –0.8 –1.5 –2.5 µA
V
SSARM
SS Pin Arming Threshold V
SS
, Ramping Positive Until Short-Circuit 3.8 4.5 V
Latch-Off is Armed
V
SSLO
SS Pin Latch-Off Threshold V
SS
, Ramping Negative 3.3 V
I
SCL
SS Discharge Current Soft-Short Condition V
EAIN
= 0.375V, V
SS
= 4.5V –5 –1.5 µA
I
SDLHO
Shutdown Latch Disable Current V
EAIN
= 0.375V, V
SS
= 4.5V 1.5 5 µA
I
SENSE
SENSE Pins Source Current SENSE1
+
, SENSE1
–
, SENSE2
+
, SENSE2
–
,1320µA
SENSE3
+
, SENSE3
–
All Equal 1.2V; Current at Each Pin
DF
MAX
Maximum Duty Factor In Dropout 95 98.5 %
TG t
R,
t
F
Top Gate Rise Time C
LOAD
= 3300pF 30 90 ns
Top Gate Fall Time C
LOAD
= 3300pF 40 90 ns
BG t
R,
t
F
Bottom Gate Rise Time C
LOAD
= 3300pF 30 90 ns
Bottom Gate Fall Time C
LOAD
= 3300pF 20 90 ns
TG/BG t
1D
Top Gate Off to Bottom Gate On Delay All Controllers, C
LOAD
= 3300pF Each Driver 60 ns
Synchronous Switch-On Delay Time
BG/TG t
2D
Bottom Gate Off to Top Gate On Delay All Controllers, C
LOAD
= 3300pF Each Driver 60 ns
Top Switch-On Delay Time
t
ON(MIN)
Minimum On-Time Tested with a Square Wave (Note 5) 120 ns
VID Parameters
VID
IL
Maximum Low Level Input Voltage 0.8 V
VID
IH
Minimum High Level Input Voltage 2 V
VID
PULLUP
VID0 to VID4 Internal Pull-Up 150 kΩ
Resistance
ATTEN
ERR
VID0 to VID4 (Note 6) ● –0.25 0.25 %
Power Good Output Indication
V
PGL
PGOOD Voltage Output Low I
PGOOD
= 2mA 0.1 0.3 V
I
PGOOD
PGOOD Output Leakage V
PGOOD
= 5V ±1 µA
PGOOD Trip Thesholds V
DIFFOUT
with Respect to Set Output Voltage,
V
PGTHNEG
V
DIFFOUT
Ramping Negative VID Code = 10011 –7 –10 –14 %
V
PGTHPOS
V
DIFFOUT
Ramping Positive PGOOD Goes Low After V
UVDLY
Delay 7 10 14 %
t
PGBLNK
Power Good Blanking After VID Changes Outside PGOOD Window 120 µs
