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LTC3733CG#TRPBF

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22
LTC3733/LTC3733-1
3733f
APPLICATIO S I FOR ATIO
WUUU
The loop filter components (C
LP
, R
LP
) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
=10k and C
LP
ranges from
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
t
V
Vf
ON MIN
OUT
IN
()
<
()
If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
The minimum on-time for the IC is generally about 120ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.
As a general rule, keep
the
inductor ripple current equal to or greater than 30%
of I
OUT(MAX)
at V
IN(MAX)
.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
• ESR, where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time, V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The I
TH
external com-
ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.
23
LTC3733/LTC3733-1
3733f
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C
LOAD
is greater
than 2% of C
OUT
, the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 • R
SENSE
• C
LOAD
. Thus a 250µF capacitor and a 2mΩ
R
SENSE
resistor would require a 500µs rise time, limiting
the charging current to about 1A.
Design Example (Using Three Phases)
As a design example, assume V
IN
= 12V(nominal), V
IN
=
20V(max), V
OUT
= 1.3V, I
MAX
= 45A and f = 400kHz. The
inductance value is chosen first based upon a 30% ripple
current assumption. The highest value of ripple current in
each output stage occurs at the maximum input voltage.
L
V
fI
V
V
V
kHz A
V
V
H
OUT OUT
IN
=
∆
()
−
=
()()()
−
≥
µ
1
13
400 30 15
1
13
20
068
.
%
.
.
Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.
R
SENSE1,
R
SENSE2
and R
SENSE3
can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:
R
mV
A
SENSE
=
+
=Ω
65
15 1
34
2
0 0037
%
.
Use a commonly available 0.003Ω sense resistor.
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V
CC
:
t
V
Vf
V
V kHz
ns
ON MIN
OUT
IN MAX
()
=
()
=
()
=
()
.13
20 400
162
APPLICATIO S I FOR ATIO
WUUU
24
LTC3733/LTC3733-1
3733f
The output voltage will be set by the VID code according
to Table 1.
The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, R
DS(ON)
= 7mΩ, C
MILLER
= 15nC/15V = 1000pF. At maximum input
voltage with T(estimated) = 50°C:
P
V
V
CC
A
pF
VV V
kHz W
MAIN
≈
()
+
()
°− °
()
[]
+
()
()()
Ω
()( )
+
()
=
18
20
15 1 0 005 50 25
0 007 20
45
23
2 1000
1
518
1
18
400 2 2
2
2
.
.
.
–. .
.
Ω
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P
VV
V
AW
SYNC
=
−
()()
Ω
()
=
20 1 3
20
15 1 25 0 007 1 84
2
.
.. .
A short circuit to ground will result in a folded back current
of:
I
mV
m
ns V
H
A
SC
≈
+
()
Ω
+
()
µ
=
25
23
1
2
150 20
06
75
.
.
with a typical value of R
DS(ON)
and d = (0.005/°C)(50°C) =
0.25. The resulting power dissipated in the bottom MOSFET
is:
P
SYNC
= (7.5A)
2
(1.25)(0.007Ω) ≈ 0.5W
which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi-
pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
APPLICATIO S I FOR ATIO
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IC. These items are also illustrated graphically in the layout
diagram of Figure 10. Check the following in the PC layout:
1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect-
ing to the PGND pin and then continuing on to the (–) plates
of C
IN
and
C
OUT
. The V
CC
decoupling capacitor should be
placed immediately adjacent to the IC between the V
CC
pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10uF of ceramic, tantalum
or other very low ESR capacitance is recommended in or-
der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of C
IN
, which
should have as short lead lengths as possible.
2) Does the IC IN
+
pin connect to the (+) plates of C
OUT
?
A 30pF to 300pF feedforward capacitor between the
DIFFOUT and EAIN pins should be placed as close as
possible to the IC.
3) Are the SENSE
–
and SENSE
+
printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE
+
and SENSE
–
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE
–
and SENSE
+
pins to the pads
of the sense resistor as illustrated in Figure 11.
4) Do the (+) plates of C
IN
connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes. Ideally the
SWITCH, BOOST and TG printed circuit traces should be
routed away and separated from the IC and the “quiet” side
of the IC.
6) The filter capacitors between the I
TH
and SGND pins
should be as close as possible to the pins of the IC.
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LTC3733CG#TRPBF

Mfr. #:
Buy LTC3733CG#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3-Phase, AMD 5-Bit VID, 600kHz Sync. Buck Switching Controller
Lifecycle:
New from this manufacturer.
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