25
LTC3733/LTC3733-1
3733f
APPLICATIO S I FOR ATIO
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Figure 10. Branch Current Waveforms
+
R
IN
V
IN
V
OUT
C
IN
BOLD LINES INDICATE HIGH,
SWITCHING CURRENT LINES.
KEEP LINES TO A MININMUM
LENGTH
+
C
OUT
D3
D2
SW2
D1
L1
SW1
R
SENSE1
L2
R
SENSE2
L3
SW3
R
SENSE3
3732 F10
R
L
Figure 11. Kelvin Sensing R
SENSE
SENSE
+
LTC3733
1000pF
INDUCTOR
OUTPUT CAPACITOR
SENSE
RESISTOR
3733 F11
SENSE
26
LTC3733/LTC3733-1
3733f
Figure 10 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec-
tric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current
The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 12 graphically
illustrates the principle.
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Figure 12. Single and Polyphase Current Waveforms
SW V
SINGLE PHASE
TRIPLE PHASE
I
CIN
I
COUT
SW1 V
SW2 V
SW3 V
I
L1
I
L2
I
L3
I
CIN
I
COUT
3732 F12
27
LTC3733/LTC3733-1
3733f
APPLICATIO S I FOR ATIO
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The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.
Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
OUT
/L discharge currents
term from the stages that has their bottom MOSFETs on
subtract current from the (V
CC
– V
OUT
)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:
I
P-P
=
()()
()
>
V
fL
DC V V
OUT
IN OUT
13 3
The ripple frequency is also increased by three, further
reducing the required output capacitance when V
CC
< 3V
OUT
as illustrated in Figure 4.
Efficiency Calculation
To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R
DS(ON)
, induc-
tor resistance R
L
, the sense resistance R
SENSE
and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:
Main MOSFET R
DS(ON)
= 7m (9m at 90°C)
Sync MOSFET R
DS(ON)
= 7m (9m at 90°C)
C
INESR
= 20m
C
OUTESR
= 3m
R
L
= 2.5m
R
SENSE
= 3m
V
SCHOTTKY
= 0.8V at 15A (0.7V at 90°C)
V
OUT
= 1.3V
V
IN
= 12V
I
MAX
= 0.8V at 15A (0.7V at 90°C)
δ = 0.01%°C
N = 3
f = 400kHz
The main MOSFET is on for the duty factor V
OUT
/V
IN
and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V
OUT
/V
IN
). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
I
OUT
is used to simplify the calaculations. The equation
below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.

LTC3733CG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3-Phase, AMD 5-Bit VID, 600kHz Sync. Buck Switching Controller
Lifecycle:
New from this manufacturer.
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