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CY8C4125PVA-482

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
Automotive PSoC
®
4: PSoC 4100
Family Datasheet
Document Number: 001-93576 Rev. *E Page 7 of 36
GPIO
PSoC 4100 has 24 GPIOs. The GPIO block implements the
following:
■ Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes).
■ Selectable slew rates for dV/dt related noise control to improve
EMI.
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal
multiplexing complexity.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4100).
Special Function Peripherals
LCD Segment Drive
The PSoC 4100 has an LCD controller which can drive up to four
commons and up to 32 segments. It uses full digital methods to
drive the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as digital
correlation and PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
PWM pertains to driving the panel with PWM signals to
effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired
LCD voltage. This method results in higher power consumption
but can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in the PSoC 4100 through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
The CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
Automotive PSoC
®
4: PSoC 4100
Family Datasheet
Document Number: 001-93576 Rev. *E Page 8 of 36
Pinouts
The following is the pin-list for PSoC 4100. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional
external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD
CapSense and Analog Mux Bus connections.
Notes:
1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively.
2. P3.2 and P3.3 are SWD pins after boot (reset).
Descriptions of the pin functions are as follows:
VDDD
: Power supply for both analog and digital sections (where there is no V
DDA
pin).
Pins 28-SSOP Alternate Functions for Pins
Pin Description
Name Type Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4
VSSD Power DN – – – – – – Digital Ground
P2.2 GPIO 5 P2.2 sarmux.2 – – – – Port 2 Pin 2: gpio, lcd, csd, sarmux
P2.3 GPIO 6 P2.3 sarmux.3 – – – – Port 2 Pin 3: gpio, lcd, csd, sarmux
P2.4 GPIO 7 P2.4 sarmux.4 tcpwm0_p[1] – – – Port 2 Pin 4: gpio, lcd, csd, sarmux,
pwm
P2.5 GPIO 8 P2.5 sarmux.5 tcpwm0_n[1] – – – Port 2 Pin 5: gpio, lcd, csd, sarmux,
pwm
P2.6 GPIO 9 P2.6 sarmux.6 tcpwm1_p[1] – – – Port 2 Pin 6: gpio, lcd, csd, sarmux,
pwm
P2.7 GPIO 10 P2.7 sarmux.7 tcpwm1_n[1] – – – Port 2 Pin 7: gpio, lcd, csd, sarmux,
pwm
P3.0 GPIO 11 P3.0 – tcpwm0_p[0] scb1_uart_rx[0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm,
scb1
P3.1 GPIO 12 P3.1 – tcpwm0_n[0] scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm,
scb1
P3.2 GPIO 13 P3.2 – tcpwm1_p[0] – swd_io scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm,
scb1, swd
P3.3 GPIO 14 P3.3 – tcpwm1_n[0] – swd_clk scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm,
scb1, swd
P4.0 GPIO 15 P4.0 – – scb0_uart_rx scb0_i2c_scl scb0_spi_mosi Port 4 Pin 0: gpio, lcd, csd, scb0
P4.1 GPIO 16 P4.1 – – scb0_uart_tx scb0_i2c_sda scb0_spi_miso Port 4 Pin 1: gpio, lcd, csd, scb0
P4.2 GPIO 17 P4.2 csd_c_mod – – – scb0_spi_clk Port 4 Pin 2: gpio, lcd, csd, scb0
P4.3 GPIO 18 P4.3 csd_c_sh_tan
k
– – – scb0_spi_ssel_0 Port 4 Pin 3: gpio, lcd, csd, scb0
P0.0 GPIO 19 P0.0 comp1_inp – – – scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0,
comp
P0.1 GPIO 20 P0.1 comp1_inn – – – scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0,
comp
P0.2 GPIO 21 P0.2 comp2_inp – – – scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0,
comp
P0.3 GPIO 22 P0.3 comp2_inn – – – – Port 0 Pin 3: gpio, lcd, csd, comp
P0.6 GPIO 23 P0.6 – ext_clk – – scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1,
ext_clk
P0.7 GPIO 24 P0.7 – – – wakeup scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1,
wakeup
XRES XRES 25 XRES – – – – – Chip reset, active low
VCCD Power 26 VCCD – – – – – Regulated supply, connect to 1 µF
cap or 1.8 V
VDDD Power 27 VDDD – – – – – Common power supply (Analog &
Digital) 1.8 V–5.5 V
VSSA Power 28(DN) VSS – – – – – Analog Ground
P1.0 GPIO 1 P1.0 ctb.oa0.inp tcpwm2_p[1] – – – Port 1 Pin 0: gpio, lcd, csd, ctb, pwm
P1.1 GPIO 2 P1.1 ctb.oa0.inm tcpwm2_n[1] – – – Port 1 Pin 1: gpio, lcd, csd, ctb, pwm
P1.2 GPIO 3 P1.2 ctb.oa0.out tcpwm3_p[1] – – – Port 1 Pin 2: gpio, lcd, csd, ctb, pwm
P1.7 GPIO 4 P1.7 ctb.oa1.inp_a
lt ext_vref
–– –
– Port 1 Pin 7: gpio, lcd, csd, ext_ref
Automotive PSoC
®
4: PSoC 4100
Family Datasheet
Document Number: 001-93576 Rev. *E Page 9 of 36
VDDA: Analog V
DD
pin where package pins allow; shorted to V
DDD
otherwise.
VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise
VSS: Ground pin.
VCCD: Regulated Digital supply (1.8 V ±5%).
Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS
A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals.
The following package is supported: 28-pin SSOP.
Figure 3. 28-pin SSOP pinout
(GPIO)P0[1]
SSOP
(Top View)
10
11
(GPIO)P1[2]
28
27
26
25
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
(GPIO)P1[1]
(GPIO)P1[7]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P3[0]
(GPIO)P4[3]
(GPIO)P0[0]
(GPIO)P0[2]
(GPIO)P0[3]
(GPIO)P0[6]
(GPIO)P0[7]
XRES
VDDD
VSS
1
12
13
14
(GPIO)P1[0]
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P4[2]
VCCD
(GPIO)P4[1]
(GPIO)P4[0]
16
15
24
(GPIO)P2[7]
(GPIO)P3[3]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

CY8C4125PVA-482

Mfr. #:
Buy CY8C4125PVA-482
Manufacturer:
Cypress Semiconductor
Description:
Lifecycle:
New from this manufacturer.
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