13
Rev. 2.00
XRD98L61
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Clock
SPIXopt
Default 0 0 0 0 0 0 0 0 0 0
Clock Register (Reg. 10, Address 001010)
The Clock register is used to set various clocking options.
CLKtest=0, Normal operation.
CLKtest=1, Exar test mode - Do not use.
Nullamp=0, Normal operation.
Nullamp=1, Exar test mode - Do not use.
CMtest=0, Normal operation.
CMtest=1, Exar test mode - Do not use.
Fastclk=0, Normal operation.
Fastclk=1, Exar test mode - Do not use.
CLAMPopt=0, DC Restore bias is on only during CLAMP.
CLAMPopt=1, DC Restore bias is always ON.
OneShot=0, CAL defines OB pixels. Clamp controls DC restore.
OneShot=1, CAL controls DC restore and defines OB pixels. CLAMP used for VS reject.
ClampCal=0, CLAMP at start of line, CAL at end of line (affects VS reject).
ClampCal=1, CAL at start of line, CLAMP at end of line (affects VS reject).
SPIXopt=0, φ2 starts DelayA[5:3] + DelayB[8:6] after SBLK trailing edge
SPIXopt=1, φ2 starts DelayB[2:0] after SPIX pin leading edge.
RSTreject=0, Reset reject switch (φ3) not clocked, always on.
RSTreject=1, Reset reject switch (φ3) clocked.
VSreject=0, Vertical Shift Reject is inactive.
VSreject=1, Vertical Shift Reject is active.
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Polarity SBLKpol SPIXpol CALpol CLAMPpol *Reserved ADCpol
Default
0
0
0
0
0
0
0
0
0
0
Polarity Register (Reg. 9, Address 001001)
The Polarity register is used to set the polarity for the 6 input clock signals.
For each clock: polarity bit=0 sets clock active low, polarity bit=1 sets clock active high.
NOTE: *Reserved Test Register bit. Used for factory test only. Please do not modify.
