XRD98L61
26
Rev. 2.00
Figure 14. Pixel Timing Showing Pipeline Delay
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchro-
nized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the
coresponding data is available at the digital output.
SPIXopt
In the default case shown in Figure 15, SPIXopt=0, the
internal sample video switches turn ON a programmed
delay after the SBLK pulse ends, and turn OFF at the
end of the SPIX pulse. The turn ON delay is pro-
grammed by DelayB[8:6].
When SPIXopt = 1, the internal SPIX switches are
controlled only by the SPIX pulse. This mode is
intended for camera systems where the designer has
the ability to externally fine tune both the rising and
falling edges of SPIX to achieve optimum performance
(see Figure 16).
CCD
Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
DB[11:0]
Sample
PGAout
Sample
Black
Sample
Video
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bits
1 & 0
Error
Correction
Pixel N
Pixel N
Pixel N+1
Pixel N-1Pixel N-2Pixel N-3Pixel N-4Pixel N-5Pixel N-6Pixel N-7
7.5 Pixel Pipeline Delay
Pixel N-8
t
DL
