XRD98L61
32
Rev. 2.00
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels Vertical Shift
Dummy &
OB pixels
CAL
Internal
DC restore time
CCD
Signal
Active Video pixels
t
CAL
4 pixels
CLAMP
(vertical shift)
Disconnect CDS from
input pins
Internal Black Level
calibration time
t
CAL
- 4 pixels
Minimum 5 Pixels
Figure 22. Line Rate Timing with OneShot=1 & VSreject=1
SETTING POWER AND PERFORMANCE WITH Rext
The power and performance levels of the XRD98L61
are set by the value of Rext. Rext sets the current bias
level for the entire chip. Rext is connected between pin
39 (ExtRef) and analog ground (see Figure 23). This
resistor should be placed as close as possible to the
pin and routed directly to a ground plane in a PCB
layout. A surface mount carbon resistor is recom-
mended.
Increasing values of Rext decrease the power, linearity
and noise performance of the XRD98L61. Lowering the
value of Rext increases linearity and noise perfor-
mance while increasing power. The tested default
value for Rext is 30KOhms.
In order to match system to system performance and
set consistent manufacturable performance levels
between cameras, it is recommended that the Rext
resistor have <1% tolerance.
Digital-to-Analog Converters
There are two voltage output, 8-bit resolution, Digital-
to-Analog Converters (DACs) which can be used for a
variety of purposes, and are controlled via the serial
interface. On power up, these DACs are disabled. To
activate them, you must write a "0" to the DAC0pd and
DAC1pd bits in the Control register.
