XRD98L61
22
Rev. 2.00
ADC Data
Clipper Output
0 40962048511
0
511
4096
Figure 10. Hot Pixel Clipper
Pixel Averager
After the clipper, the logic takes an average of Optical
Black pixels. The number of pixels to be averaged can
be selected as one of the following: 4, 8, 16, 32, 64, 128,
256, or 512. The AVG[2:0] bits in the Calibration
register are used to program the number of pixels to
average. This averaging function filters out noise and
prevents image artifacts. The calibration logic will
average OB pixels over as many lines as required to
get the programmed number of pixels to average.
Table 4. Programming the Pixel Averager
Offset Difference
Next, the Offset register value, OB[7:0], is subtracted
from the OB pixel average. If the difference is positive,
the offset DACs are adjusted to reduce the effective
ADC output code. If the difference is negative, the
offset DACs are adjusted to increase the effective
ADC output code. The FAST_CAL and DNS options
will affect how the DAC adjustments are made.
Coarse & Fine Accumulators
The Coarse and Fine Accumulators are the registers
which hold the digital codes for the Coarse and Fine
Offset DACs. The Offset DAC adjustments are made
by adding or subtracting to the value in the Fine
accumulator. If there is an overflow or underflow in the
Fine Accumulator, the Fine Accumulator is reset to its
mid-scale value, and the Coarse Accumulator is
incremented or decremented accordingly.
Hot Pixel Clipper
CCD’s occasionally have hot pixels. These are defec-
tive pixels, which always output a bright level. To
ensure the Black Level is not affected by hot pixels in
the OB area, the Hot Pixel Clipper limits pixel data from
the ADC to a maximum value of 511 (1FFh). This
clipping only affects the data used by the internal
calibration logic. Data on the ADC output bus,
DB[11:0], is not clipped.
AVG[2] AVG[1] AVG[0] # of Pixels to Average
0 0 0 4 (Not recommended)
0 0 1 8 (Not recommended)
0 1 0 16 (Not recommended)
0 1 1 32
1 0 0 64
1 0 1 128 (default)
1 1 0 256
1
1
1
512
23
Rev. 2.00
XRD98L61
CALIBRATION OPTIONS
Fast Cal
The purpose of this option is to reduce the amount of
time required for initial convergence of the calibration
feedback system. The feedback system is designed to
have a slow response time to avoid introducing image
artifacts. The slow response time is achieved by
averaging many OB pixels and by limiting the Fine
accumulator changes to ± 1 count at a time (FDAC lsb
= ½ ADC lsb). The FastCal option maintains this slow
response while the difference between the averaged
ADC data and the Offset Code is small, but when the
difference is larger than ±128 lsb’s, the coarse accu-
mulator takes a step. The actual step size depends on
the PGA Gain code, and is set such that the step will
cause no more than a 128 LSB change in the ADC
output.
To activate the FastCal mode ,write a “1” to the FastCal
bit in the Calibration register. By default, the FastCal
mode is active.
Difference [ADC lsb's]
Offset Adjustment [ADC LSBs]
0-1 +1-128 +128
0
+0.5
-0.5
Fine DAC Steps
Coarse DAC steps
Figure 11. Calibration in FastCal
(Speed Up) Mode
DNS[1] DNS[0] DNS Filter Width
0 0 OFF (default)
0 1 Narrow
1 0 Medium
1 1 Wide
Digital Noise Suppression (DNS Filter)
The purpose of this option is to eliminate small
changes in the Black Level offset by making the
calibration system less sensitive to small changes in
the measured offset. In this mode, the user has the
option of selecting from three filter settings;see Table 5.
Table 5. DNS Threshold Programming
To activate the Digital Noise Suppression mode, write
to the DNS[1:0] bits in the Calibration register.By
default, the Digital Noise Suppression is ON and set to
the wide filter width.
Hold Mode
The purpose of this mode is to prevent any changes in
the Fine or Coarse accumulators. This mode is in-
tended to optimize digital still camera applications
(DSC). The idea is to first run the calibration normally
so the Fine and Coarse accumulators converge on the
correct values to achieve the programmed Offset
Code. Then, just before acquiring the final image data,
activate the Hold mode. This will ensure the black level
offset of the CDS/PGA does not change while the final
image is being transferred out of the CCD. Once the
image has been acquired from the CCD, turn off the
Hold mode so the chip can continue to compensate for
any changes in offset due to temperature drift or other
effects.
To activate the Hold mode, write a “1” to the Hold bit in
the Calibration register. By default, the Hold mode is
not active.
XRD98L61
24
Rev. 2.00
OB PIXEL CALIBRATION
Line Mode Calibration
In the Line mode, OB pixels are sampled when CAL is
active. CAL can be programmed to be active high or
active low. Please see the Timing section for more
details about clock polarity. Averaging will span as
many lines as needed to get the number of OB pixels
programmed by AVG[2:0]. Updates to the offset DACs
occur during the Optical Black pixel time after a
complete iteration. A complete iteration includes the
pixel clipping, averaging, calculation of the offset dif-
ference, and calculation of the DAC update values.
After a complete iteration, the averager is reset, and
the logic waits for the number of lines programmed in
the “Wait A” & “Wait B” registers (WL[11:0]) before
starting the next iteration.
Figure 12. Clock Polarity and Aperture Delays
CLOCK BASICS
There are five clock signals: SBLK, SPIX, ADCLK,
CLAMP, and CAL.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sam-
pling the PGA output.
PolaritySBLK
SPIX
ADCLK
CAL
CLAMP
Aperture
Delays
Clock Logic
AFE
ADC
Calibration
CLOCK POLARITY
Each of the five clocks has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, reset bit or reset pin), all clocks default to
active low.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. This allows manual adjustment of
offset in applications such as digital copiers and high
speed scanners. In Manual mode, the Coarse accu-
mulator is programmed by writing to the CDAC register;
the Fine accumulator is programmed by writing to the
FDAC register. The Coarse accumulator is a 9 bit
register. The Fine accumulator is a 10 bit register.
To activate the Manual mode, write a ”1” to the ManCal
bit in the Calibration register. By default, the Manual
mode is not active.
The line rate clocks are CLAMP & CAL. CLAMP
controls the DC restore function for the external AC
coupling capacitors. CAL controls the Black level
calibration by defining the OB pixels at the start or end
of each line. In the One Shot mode (CAL only),
CLAMP is used to define the vertical shift period
between lines.

XRD98L61AIV-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
IC CCD DIGITIZER 12BIT 48TQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet