70V9279L12PRFI Datasheet 70V9269L12PRFGI, 70V9279L7PRFG, 70V9269S12PRFGI | P1-P3

OCTOBER 2008

DSC 3743/11

1

Functional Block Diagram

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 6.5/7.5/9/12/15ns (max.)

– Industrial: 7.5ns (max.)

◆

Low-power operation

– IDT70V9279/69S

Active: 429mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V9279/69L

Active: 429mW (typ.)

Standby: 1.32mW (typ.)

◆

Flow-through or Pipelined output mode on either port via

the FT/PIPE pin

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 4ns setup to clock and 1ns hold on all control, data,

and address inputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 10ns cycle time, 100MHz operation in Pipelined output mode

◆

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

◆

LVTTL- compatible, single 3.3V (±0.3V) power supply

◆

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Available in a 128-pin Thin Quad Flatpack (TQFP) package

HIGH-SPEED 3.3V

32/16K x 16

SYNCHRONOUS

DUAL-PORT STATIC RAM

IDT70V9279/69S/L

1a 0a

1b 0b

0/1

ba

1

0/1

0

0a 1a

0b 1b

0/1

ab

1

0/1

0

FT

/PIPE

R

R/

W

R

UB

R

LB

R

CE

0R

OE

R

CE

1R

I/O

Control

MEMORY

ARRAY

I/O

Control

Counter/

Address

Reg.

3743 drw 01

A

14R

(1)

A

0R

CLK

R

ADS

R

CNTE N

R

CNTRS T

R

I

/O

8L

-I/O

15L

I/O

0L

-I/O

7L

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

A

0L

CLK

L

ADS

L

A

14L

(1)

CNTEN

L

CNTRS T

L

Counter/

Address

Reg.

R/

W

L

UB

L

LB

L

CE

0L

OE

L

CE

1L

,

FT

/PIPE

L

NOTE:

1. A

14X is a NC for IDT70V9269.

◆

Green parts available, see ordering information

6.42

IDT70V9279/69S/L

High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

102

101

100

99

98

97

96

95

94

93

92

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

70

69

68

67

66

65

91

71

I

/

O

1

R

V

s

I

/

O

1

5

R

I

/

O

1

4

R

I

/

O

1

3

R

I

/

O

1

2

R

V

S

A

1

0

R

A

1

R

A

1

2

R

A

1

3

R

A

1

4

R

(

1

)

F

T

/

P

I

P

E

R

N

/

C

N

/

C

N

/

C

L

B

R

U

B

R

C

E

0

R

C

E

1

R

C

N

T

R

S

T

R

V

D

R

/

W

R

O

E

R

V

D

V

D

N/C

A

9R

A

8R

A

7R

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

N/C

CNTEN

R

CLK

R

ADS

R

V

SS

V

DD

N/C

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

N/C

I/O

10L

I/O

9L

V

DD

N/C

I/O

8L

N/C

V

DD

I/O

7L

I/O

6L

I/O

5L

I/O

4L

V

SS

I/O

3L

I/O

2L

V

SS

I/O

1L

I/O

0L

V

DD

V

SS

I/O

0R

I/O

2R

I/O

1R

V

SS

I/O

4R

I/O

5R

I/O

6R

V

DD

I/O

7R

N/C

I/O

8R

N/C

V

SS

I/O

9R

I/O

10R

V

DD

I/O

3R

70V9279/69PRF

PK-128

(5)

128-Pin TQFP

Top View

(6)

3743 drw 02

A

1

0

L

A

1

L

A

1

2

L

A

1

3

L

A

1

4

L

(

1

)

N

/

C

N

/

C

N

/

C

L

B

L

U

B

L

C

E

0

L

C

E

1

L

V

D

V

S

R

/

W

L

O

E

L

F

T

/

P

I

P

E

L

V

S

I

/

O

1

5

L

I

/

O

1

4

L

I

/

O

1

3

L

I

/

O

1

2

L

V

D

V

S

I

/

O

1

L

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

5

1

5

2

5

3

5

4

5

6

5

7

5

8

5

9

6

0

6

1

6

2

6

3

6

4

1

2

8

1

2

7

1

2

6

1

2

5

1

2

4

1

2

3

1

2

1

2

1

2

0

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

0

1

0

9

1

0

8

1

0

7

1

0

6

1

0

5

1

0

4

1

0

3

CNTEN

L

CLK

L

ADS

L

N/C

C

N

T

R

S

T

L

01/15/04

Description:

The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to

allow simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold times.

The timing latitude provided by this approach allows systems to be

designed with very short cycle times.

Pin Configuration

(2,3,4)

NOTES:

1. A

14X is a NC for IDT70V9269.

2. All V

DD pins must be connected to power supply.

3. All V

SS pins must be connected to ground.

4. Package body is approximately 14mm x 20mm x 1.4mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT70V9279/69 has been optimized for

applications having unidirectional or bidirectional data flow in bursts. An

automatic power down feature, controlled by CE0 and CE1, permits the

on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 429mW of power.

6.42

IDT70V9279/69S/L

High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

3

NOTES:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4 LB and UB are single buffered regardless of state of FT/PIPE.

5. CEo and CE

1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

Truth Table I—Read/Write and Enable Control

(1,2,3)

Pin Names

Left Port Right Port Names

CE

0L,

CE

1L

CE

0R,

CE

1R

Chip Enables

(3)

R/W

L

R/W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

- A

14L

(1)

A

0R

- A

14R

(1)

Address

I/O

0L

- I/O

15L

I/O

0R

- I/O

15R

Data Input/Output

CLK

L

CLK

R

Clock

UB

L

UB

R

Upper Byte Select

(2)

LB

L

LB

R

Lower Byte Select

(2)

ADS

L

ADS

R

Address Strobe Enable

CNTEN

L

CNTEN

R

Counter Enable

CNTRST

L

CNTRST

R

Counter Reset

FT/PIPE

L

FT/PIPE

R

Flow-Through / Pipeline

V

DD

Power (3.3V)

V

SS

Ground (0V)

3743 tbl 01

OE

CLK

CE

0

(5)

CE

1

(5)

UB

(4)

LB

(4)

R/W

Upper Byte

I/O

8-15

Lower Byte

I/O

0-7

MODE

X

↑

H X X X X High-Z High-Z Deselected–Power Down

X

↑

X L X X X High-Z High-Z Deselected–Power Down

X

↑

L H H H X High-Z High-Z Both Bytes Deselected

X

↑

LHLHL D

IN

High-Z Write to Upper Byte Only

X

↑

LHHLL High-Z DATA

IN

Write to Lower Byte Only

X

↑

LHLLL DATA

IN

DATA

IN

Write to Both Bytes

L

↑

LHLHH DATA

OUT

High-Z Read Upper Byte Only

L

↑

LHHLH High-Z DATA

OUT

Read Lower Byte Only

L

↑

LHLLH DATA

OUT

DATA

OUT

Read Both Bytes

H

↑

L H L L X High-Z High-Z Outputs Disabled

3743 tbl 02

NOTES:

1. Address A

14X is a NC for IDT70V9269.

2. LB and UB are single buffered regardless of state of FT/PIPE.

3. CE

0 and CE1 are single buffered when FT/PIPE = VIL,

CE

0 and CE1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

70V9279L12PRFI

70V9279L12PRFI

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