6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
(3,4)
(VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (t
CYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = V
IL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
70V9279/69X6
Com'l Only
70V9279/69X7
Com'l
& Ind
70V9279/69X9
Com'l Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(2)
19
____
22
____
25
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(2)
10
____
12
____
15
____
ns
t
CH1
Clock High Time (Flow-Through)
(2)
6.5
____
7.5
____
12
____
ns
t
CL1
Clock Low Time (Flow-Through)
(2)
6.5
____
7.5
____
12
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
4
____
5
____
6
____
ns
t
CL2
Clock Low Time (Pipelined)
(2)
4
____
5
____
6
____
ns
t
R
Clock Rise Time
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3ns
t
SA
Address Setup Time 3.5
____
4
____
4
____
ns
t
HA
Address Hold Time 0
____
0
____
1
____
ns
t
SC
Chip Enable Setup Time 3.5
____
4
____
4
____
ns
t
HC
Chip Enable Hold Time 0
____
0
____
1
____
ns
t
SW
R/W Setup Time 3.5
____
4
____
4
____
ns
t
HW
R/W Hold Time 0
____
0
____
1
____
ns
t
SD
Input Data Setup Time 3.5
____
4
____
4
____
ns
t
HD
Input Data Hold Time 0
____
0
____
1
____
ns
t
SAD
ADS Setup Time
3.5
____
4
____
4
____
ns
t
HAD
ADS Hold Time
0
____
0
____
1
____
ns
t
SCN
CNTEN Setup Time
3.5
____
4
____
4
____
ns
t
HCN
CNTEN Hold Time
0
____
0
____
1
____
ns
t
SRST
CNTRST Setup Time
3.5
____
4
____
4
____
ns
t
HRST
CNTRST Hold Time
0
____
0
____
1
____
ns
t
OE
Output Enable to Data Valid
____
6.5
____
7.5
____
9ns
t
OLZ
Output Enable to Output Low-Z
(1)
2
____
2
____
2
____
ns
t
OHZ
Output Enable to Output High-Z
(1)
17 17 17ns
t
CD1
Clock to Data Valid (Flow-Through)
(2)
____
15
____
18
____
20 ns
t
CD2
Clock to Data Valid (Pipelined)
(2)
____
6.5
____
7.5
____
9ns
t
DC
Data Output Hold After Clock High 2
____
2
____
2
____
ns
t
CKHZ
Clock High to Output High-Z
(1)
292929ns
t
CKLZ
Clock High to Output Low-Z
(1)
2
____
2
____
2
____
ns
Port-to-Port Delay
t
CWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35 ns
t
CCS
Clock-to-Clock Setup Time
____
9
____
10
____
15 ns
3743 tbl 11a
