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70V9279L12PRFI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE
"X" = VIL)
(3,7)
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE
"X" = VIH)
(3,7)
An An + 1 An + 2 An + 3
t
CYC1
t
CH1
t
CL1
R/
W
ADDRESS
DATA
OUT
CE
0
CLK
OE
t
SC
t
HC
t
CD1
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
t
CKHZ
3743 drw 06
(1)
(1)
(1)
(1)
(2)
CE
1
UB, LB
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
DC
(5)
t
SC
t
HC
t
SB
t
HB
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
UB, LB
(4)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
3743 drw 07
(1)
(1)
(1)
(2)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(5)
(1 Latency)
(6)
(6)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = V
IL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE
0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATA
OUT for Qn + 2 would be disabled (High-Impedance state).
7. "
X" denotes Left or Right port. The diagram is with respect to that port.
6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of a Bank Select Pipelined Read
(1,2)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
3743 drw 08
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
(3)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
(3)
(3)
t
SC
t
HC
(3)
t
CKHZ
(3)
t
CKLZ
(3)
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9279/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = V
IL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE
0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If t
CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t
CCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
Timing Waveform of a Bank Select Flow-Through Read
(6)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
3743 drw 08a
D
0
D
3
t
CD1
t
CKLZ
t
CKHZ
(1)
(1)
D
1
DATA
OUT(B1)
t
CH1
t
CL1
CYC1
(1)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
D
2
D
4
t
CD1
t
CD1
t
CKHZ
t
DC
t
CD1
t
CKLZ
t
SC
t
HC
(1)
t
CKHZ
(1)
t
CKLZ
(1)
t
CD1
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
D
5
t
CD1
t
CKLZ
(1)
t
CKHZ
(1)
6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,3,5)
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD1
t
DC
DATA
OUT "B"
3743 drw 09
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CCS
t
DC
t
SA
t
SW
t
HA
(4)
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE
0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If t
CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t
CCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
NOTES:
1. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = V
IL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If t
CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t
CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t
CO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
CLK
"A"
R/W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
3743 drw 10
t
DC
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

70V9279L12PRFI

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IC SRAM 512K PARALLEL 128TQFP
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