Document Number: 001-86188 Rev. *E Page 12 of 22
SRAM Write Cycle
t
WC
t
WC
Write cycle time 110 – ns
t
CA
– Chip enable active time 55 – ns
t
CW
t
SCE
Chip enable to write enable HIGH 55 – ns
t
PC
– Pre-charge time 55 – ns
t
PWC
– Page mode write enable cycle time 25 – ns
t
WP
t
PWE
Write enable pulse width 16 – ns
t
AS
t
SA
Address setup time (to CE LOW) 0 – ns
t
ASP
– Page mode address setup time (to WE LOW) 8 – ns
t
AHP
– Page mode address hold time (to WE LOW) 15 – ns
t
WLC
t
PWE
Write enable LOW to chip disabled 25 – ns
t
BLC
t
BW
UB, LB LOW to chip disabled 25 – ns
t
WLA
– Write enable LOW to A
17-2
change 25 – ns
t
AWH
– A
17-2
change to write enable HIGH 110 – ns
t
BS
UB, LB setup time (to CE LOW) 2 – ns
t
BH
UB, LB holdp time (to CE HIGH) 0 – ns
t
DS
t
SD
Data input setup time 14 – ns
t
DH
t
HD
Data input hold time 0 – ns
t
WZ
[6, 7]
t
HZWE
Write enable LOW to output HI-Z – 10 ns
t
WX
[7]
– Write enable HIGH to output driven 10 – ns
t
WS
[8]
– Write enable to CE LOW setup time 0 – ns
t
WH
[8]
– Write enable to CE HIGH hold time 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters
[3]
Description Min Max Unit
Cypress
Parameter
Alt Parameter
Notes
6. t
WZ
is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
7. This parameter is characterized but not 100% tested.
8. The relationship between CE
and WE determines if a CE- or WE-controlled write occurs. The parameters t
WS
and t
WH
are not tested.
