Document Number: 001-86188 Rev. *E Page 16 of 22
Power Cycle and Sleep Mode Timing
Over the Operating Range
Parameter Description Min Max Unit
t
PU
Power-up (after V
DD
min. is reached) to first access time 450 – µs
t
PD
Last write (WE HIGH) to power down time 0 – µs
t
VR
[12, 13]
V
DD
power-up ramp rate 50 – µs/V
t
VF
[12, 13]
V
DD
power-down ramp rate 100 – µs/V
t
ZZH
ZZ active to DQ HI-Z time – 20 ns
t
WEZZ
Last write to sleep mode entry time 0 – µs
t
ZZL
ZZ active LOW time 1 – µs
t
ZZEN
Sleep mode entry time (ZZ LOW to CE don’t care) – 0 µs
t
ZZEX
Sleep mode exit time (ZZ HIGH to 1
st
access after wakeup) – 450 µs
Figure 16. Power Cycle and Sleep Mode Timing
ZZ
V
DD
min.
V
DD
WE
t
PD
CE
DQ
R/W
Allowed
t
WEZZ
t
PU
D out
t
ZZH
D in
t
ZZEX
R/W
Allowed
t
ZZEN
R/W
Allowed
t
ZZEX
V
DD
min.
t
ZZL
t
VR
t
VF
Note
12. Slope measured at any point on the V
DD
waveform.
13. Cypress cannot test or characterize all V
DD
power ramp profiles. The behavior of the internal circuits is difficult to predict when V
DD
is below the level of a transistor
threshold voltage. Cypress strongly recommends that V
DD
power up faster than 100 ms through the range of 0.4 V to 1.0 V.
