7
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register pointer,
nor execute a write.
The contents of the offset registers can be read on the output lines when the
LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-
to-HIGH transition of the read clock (RCLK). The act of reading the control
registers employs a dedicated read offset register pointer. (The read and write
pointers operate independently).
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FL)
FL is grounded to indicate operation in the Single Device or Width Expansion
mode. In the Depth Expansion configuration, FL is grounded to indicate it is the
first device loaded and is set to HIGH for all other devices in the Daisy Chain.
(See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXI)
This is a dual purpose pin. WXI is grounded to indicate operation in the Single
Device or Width Expansion mode. WXI is connected to Write Expansion Out
(WXO) of the previous device in the Daisy Chain Depth Expansion mode.
READ EXPANSION INPUT (RXI)
This is a dual purpose pin. RXI is grounded to indicate operation in the Single
Device or Width Expansion mode. RXI is connected to Read Expansion Out
(RXO) of the previous device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG(FF)
When the FIFO is full, FF will go LOW, inhibiting further write operations.
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72205LB,
512 for the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the IDT72235LB
and 4,096 for the IDT72245LB.
The FF is updated on the LOW-to-HIGH transition of the write clock (WCLK).
EMPTY FLAG/ (EF)
When the FIFO is empty, EF will go LOW, inhibiting further read operations.
When EF is HIGH, the FIFO is not empty.
The EF is updated on the LOW-to-HIGH transition of the read clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW when FIFO
reaches the Almost-Full condition. If no reads are performed after Reset (RS),
the PAF will go LOW after (256-m) writes for the IDT72205LB, (512-m) writes
for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes
for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m”
is defined in the FULL offset register.
If there is no Full offset specified, the PAF will be LOW when the device is
31 away from completely full for IDT72205LB, 63 away from completely full for
IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/
72245LB.
The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock
(WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the read clock
(RCLK). Thus PAF is asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The ProgrammableAlmost-Empty Flag(PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined in
the EMPTY offset register.
If there is no Empty offset specified, the Programmable Almost-Empty Flag
(PAE) will be LOW when the device is 31 away from completely empty for
IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away
from completely empty for IDT72225LB/72235LB/72245LB.
The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock
(RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the write clock
(WCLK). Thus PAE is asynchronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are
grounded, this output acts as an indication of a half-full memory.
Number of Words in FIFO
IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB FF PAF HF PAE EF
00 0 0 0HHHLL
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
HH H LH
(n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 H H H H H
129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1,024-(m+1)) 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1))
HH L HH
(256-m)
(2)
to 255 (512-m)
(2)
to 511 (1,024-m)
(2)
to 1,023 (2,048-m)
(2)
to 2,047 (4,096-m)
(2)
to 4,095 H L L H H
256 512 1,024 2,048 4,096 L L L H H
TABLE 1 — STATUS FLAGS
NOTES:
1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127)
2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)
