SSM4321ACBZ-R7 Datasheet SSM4321ACBZ-R7, SSM4321ACBZ-RL | P16-P18

Data Sheet SSM4321

Rev. 0 | Page 15 of 24

EMI NOISE

The SSM4321 uses a proprietary modulation and spread-spectrum

technology to minimize EMI emissions from the device. For

applications that have difficulty passing FCC Class B emission tests

or experience antenna and RF sensitivity problems, the ultralow

EMI architecture of the SSM4321 significantly reduces the radiated

emissions at the Class-D outputs, particularly above 100 MHz.

EMI emission tests on the SSM4321 were performed in an FCC-

certified EMI laboratory with a 1 kHz input signal, producing

0.5 W of output power into an 8 Ω load from a 5.0 V supply. The

SSM4321 passed FCC Class B limits with 50 cm of unshielded

twisted pair speaker cable. Note that reducing the power supply

voltage greatly reduces radiated emissions.

OUTPUT CURRENT SENSING

The SSM4321 uses an external sense resistor to determine the

output current flowing to the load. As shown in Figure 1, one end

of the sense resistor is tied to one amplifier output pin (OUT+);

the other end of the sense resistor is tied to the load, which is also

connected to one sense input pin (SENSE−).

The voltage across the sense resistor is proportional to the load

current and is sent to an analog-to-digital converter (ADC) run-

ning nominally at 128 f

. The output of this ADC is downsampled

using digital filtering. The downsampled signal is output at a rate

of 8 kHz to 48 kHz on Slot 1 of the TDM bus. The 16-bit data is

in signed fractional format.

The current sense output is scaled so that an output current of

0.75 A (6 V/8 Ω) with a 200 mΩ sense resistor results in full-scale

output from the ADC. Table 7 lists the optimal sense resistor

values for commonly used output loads.

Table 7. Optimal Sense Resistor for Typical Loads

Load Value (Ω) Peak Current (A) Sense Resistor (mΩ)

8 0.75 200

4 1.5 100

3 2 75

OUTPUT VOLTAGE SENSING

The output voltage level is monitored and sent to an ADC

running nominally at 128 f

. The output of this ADC is down-

sampled using digital filtering. The downsampled signal is

output at a rate of 8 kHz to 48 kHz on Slot 2 of the TDM bus.

The 16-bit data is in signed fractional format.

PVDD SENSING

The SSM4321 contains an 8-bit ADC that measures the voltage

of the PVDD supply in real time. The output of the ADC is in

8-bit unsigned format and is presented on the 8 MSBs of Slot 3

on the TDM bus. The eight LSBs are driven low.

SSM4321 Data Sheet

Rev. 0 | Page 16 of 24

SERIAL DATA INPUT/OUTPUT

The SSM4321 includes circuitry to sense output current, output

voltage, and the PVDD supply voltage. The output current, output

voltage, and PVDD voltage are sent to ADCs. The output of these

ADCs is available on the TDM or I

S output serial port. A direct

PDM bit stream of voltage and current data (or current and PVDD

data) can also be selected.

TDM OPERATING MODE

The digitized output current, output voltage, and PVDD sense

signals can be output on a TDM serial port. This serial port is

always a slave and requires a bit clock (BCLK) and a frame

synchronization signal (FSYNC) to operate. The output data is

driven on the SDATAO/PDM_DATA pin at the IOVDD voltage.

(See the Timing Diagrams, TDM Mode section.)

The FSYNC signal operates at the desired sample rate. A rising

edge of the FSYNC signal indicates the start of a new frame. For

proper operation, this signal should be one BCLK cycle wide,

transitioning on a falling BCLK edge. The MSB of the Slot 1 data

is output on the SDATAO/PDM_DATA pin one BCLK cycle later.

The SDATAO signal should be latched on a rising edge of BCLK.

Each slot is 64 BCLK cycles wide.

The SSM4321 can drive only four slots on its output, but it can

work with 8 slots, 12 slots, or 16 slots. In this way, up to four

SSM4321 devices can use the same TDM bus. At startup, the

number of slots used is recognized automatically by the number

of BCLK cycles between FSYNC pulses. Internal clocking is

automatically generated from BCLK based on the determined

BCLK rate.

The set of four TDM slots to be driven is determined by the

configuration of the SLOT pin on the SSM4321 (see Table 8).

The value of the SLOT pin must be stable at startup.

Table 8. TDM Slot Selection

Device Setting SLOT Pin Configuration

TDM Slot 1 to Slot 4 used Tie to IOVDD

TDM Slot 5 to Slot 8 used Open

TDM Slot 9 to Slot 12 used Tie to GND

TDM Slot 13 to Slot 16 used Tie to IOVDD through a 47 kΩ resistor

The SSM4321 sets the SDATAO/PDM_DATA pin to a high

impedance state when a slot is present that is not being driven.

Connect a pull-down resistor to the SDATAO/PDM_DATA pin

so that it is always in a known state.

With a single SSM4321 operating with four slots, Slot 1 is for

the output current, Slot 2 is for the output voltage, Slot 3 is for

the PVDD supply, and Slot 4 is not driven. With more than four

slots, this pattern is repeated. Table 9 shows an example with

three SSM4321 devices and 12 TDM slots.

Table 9. TDM Output Slot Example—Three SSM4321 Devices

TDM Slot Data Present

1 Output current, Device 1

2 Output voltage, Device 1

3 PVDD voltage, Device 1

High-Z

5 Output current, Device 2

6 Output voltage, Device 2

PVDD voltage, Device 2

8 High-Z

9 Output current, Device 3

10 Output voltage, Device 3

11 PVDD voltage, Device 3

12 High-Z

S AND LEFT JUSTIFIED OPERATING MODE

An I

S or left justified output interface can be selected by reversing

the pin connections for BCLK and FSYNC; that is, the I

S LRCLK

is connected to Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S),

and the I

S BCLK is connected to Ball D2 (FSYNC_TDM/

BCLK_I2S).

The I

S interface requires 64 BCLK cycles per LRCLK cycle. The

voltage information is sent when LRCLK is low, and the current

information is sent when LRCLK is high. (See the Timing

Diagrams, I

S and Left Justified Modes section.)

The SLOT pin configures the I

S or left justified output as follows

(see Table 10).

• Selection of I

S or left justified mode.

• Output of PVDD sense information. When PVDD data is

output, eight bits are appended to the 16-bit voltage sense

data to create a 24-bit output. The 16 MSBs represent the

voltage data; the eight LSBs represent the PVDD data.

• Sample rate range. The sample rate ranges from 16 kHz

to 48 kHz. A range of 32 kHz to 48 kHz is also allowed in

low power I

S mode.

Table 10. I

S and Left Justified Slot Selection

Device Setting BCLK Setting SLOT Pin Configuration

S mode at 16 kHz to 48 kHz; voltage and current data only

64 × f

Tie to IOVDD

Left justified mode at 16 kHz to 48 kHz; voltage and current data only 64 × f

Open

S mode at 16 kHz to 48 kHz; PVDD data appended to voltage data 64 × f

Tie to GND

Left justified mode at 16 kHz to 48 kHz; PVDD data appended to voltage data 64 × f

Tie to IOVDD through a 47 kΩ resistor

Low power I

S mode at 32 kHz to 48 kHz; voltage and current data only 32 × f

or 64 × f

Tie to GND through a 47 kΩ resistor

Data Sheet SSM4321

Rev. 0 | Page 17 of 24

MULTICHIP I

S OPERATING MODE

A special multichip I

S mode is enabled when the part is wired

for TDM mode (BCLK and FSYNC not reversed) but the FSYNC

signal has a 50% duty cycle. If the FSYNC signal consists of one-

clock-cycle pulses, TDM operating mode is active instead.

The multichip I

S interface allows multiple chips to drive a single

S bus. Each chip takes control of the bus every two or four frames

(depending on the number of chips placed on the bus), allowing

a maximum of four chips on the bus. The SLOT pin assignments

determine the order of control. (See the Timing Diagrams,

Multichip I

S Mode section.)

Each frame also contains a 1-bit ID code, which is appended to

the current data in the frame. This code indicates the chip that

sent the data for that frame. Table 11 provides the mapping of

SLOT pin assignments to ID code.

Table 11. Multichip I

S Slot Selection

Chip No.

ID Code

SLOT Pin Configuration

1 0001 Tie to IOVDD

2 0010 Open

3 0100 Tie to GND

4 1000 Tie to IOVDD through a 47 kΩ resistor

The part is automatically configured for two-chip or four-chip

operation, depending on the number of chips detected on the bus.

The part starts up in four-chip operation, but after it detects that

Slot 3 and Slot 4 are unused, the part switches to two-chip oper-

ation. For two-chip operation, the first and second slots must be

used. If there are three chips on the bus, Slot 1 must be used along

with any two other slots.

Table 12 lists the FSYNC and BCLK rates that are supported in

multichip I

S mode.

Table 12. FSYNC and BCLK Rates in Multichip I

S Mode,

= 16 kHz to 48 kHz

Valid Slots FSYNC Rate BCLK Rate

1 and 2 2 × f

(32 kHz to 96 kHz)

128 × f

(2.048 MHz to 6.144 MHz)

1, 2, 3, 4 4 × f

(64 kHz to 128 kHz)

256 × f

(4.096 MHz to 12.288 MHz)

PDM OUTPUT MODE

By connecting the SLOT pin to GND through a 47 kΩ resistor,

the 1-bit PDM data from the ADCs can be output directly. In

PDM mode, a 1 MHz to 6.144 MHz clock must be provided on

Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S). PDM data is

sent on both edges of the clock and is output on Ball D1 (SDATAO/

PDM_DATA). (See the Timing Diagrams, PDM Mode section.)

In PDM mode, Ball D2 (FSYNC_TDM/BCLK_I2S) is used to

select the information that is output on the two possible channels

(see Table 13).

Table 13. FSYNC_TDM Pin Settings for PDM Mode

Output Data FSYNC_TDM Pin

Current data on rising edge;

voltage data on falling edge

Tie to IOVDD

Current data on rising edge;

PVDD data on falling edge

Tie to GND

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

SSM4321ACBZ-R7

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Manufacturer:

Analog Devices Inc.

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Audio Amplifiers Mono 2.9W Class-D w/ Digital Crnt & Vout

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SSM4321ACBZ-R7

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