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SSM4321ACBZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
SSM4321 Data Sheet
Rev. 0 | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3.
Parameter Rating
PVDD Supply Voltage 6 V
IOVDD Supply Voltage 3.6 V
Input Voltage PVDD
Common-Mode Input Voltage PVDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range
−65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 4 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Junction-to-air thermal resistance (θ
JA
) is specified for the
worst-case conditions, that is, a device soldered in a printed
circuit board (PCB) for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θ
JA
1
Unit
16-Ball, 1.74 mm × 1.74 mm WLCSP 665 °C/W
1
The θ
JA
specification is measured on a JEDEC standard 4-layer PCB.
ESD CAUTION
Data Sheet SSM4321
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
1
A
B
C
D
2 3 4
BALL A1
INDICATOR
OUT+
SENSE+
SENSE–
SDATAO/
PDM_DATA
PVDD
GND
IOVDD
BCLK_TDM/
PDM_CLK/
LRCLK_I2S
VREG
GND
IN+
IN–
OUT–
GAIN
SLOT
FSYNC_TDM/
BCLK_I2S
10752-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
A1 OUT+ Noninverting Output.
A2 OUT− Inverting Output.
A3 PVDD Amplifier Power Supply.
A4 VREG Internal LDO Regulator Output.
B1 SENSE+ Current Sense Positive Input.
B2 GAIN Gain Control Pin.
B3, B4 GND Ground.
C1 SENSE− Current Sense Negative Input.
C2 SLOT TDM Slot Selection Input.
C3 IOVDD Input/Output Digital Power Supply.
C4 IN+ Noninverting Input.
D1
SDATAO/PDM_DATA
TDM Serial Data Output/PDM Data Output.
D2 FSYNC_TDM/BCLK_I2S TDM Frame Synchronization Input/I
2
S Bit Clock Input.
D3 BCLK_TDM/PDM_CLK/
LRCLK_I2S
TDM Bit Clock Input/PDM Clock Input/I
2
S LRCLK Input.
D4 IN− Inverting Input.
SSM4321 Data Sheet
Rev. 0 | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
PVDD = 5.0 V, IOVDD = 1.8 V, f
S
= 24 kHz with I
2
S output, gain = 6 dB, T
A
= 25°C, unless otherwise noted. For R
L
= 8 Ω, use a 200 mΩ
V/I sense resistor; for R
L
= 4 Ω, use a 100 mΩ V/I sense resistor; for R
L
= 3 Ω, use a 75 mΩ V/I sense resistor.
100
10
1
0.1
0.01
0.001
0.001 1010.10.01
THD + N (%)
OUTPUT POWER (W)
PVDD = 2.5V
PVDD = 3.6V
R
L
= 8Ω + 33µH
PVDD = 5.0V
10752-103
Figure 3. THD + N vs. Output Power into 8 Ω
100
10
1
0.1
0.01
0.001
0.001 1010.10.01
THD + N (%)
OUTPUT POWER (W)
PVDD = 2.5V
PVDD = 3.6V
R
L
= 4Ω + 15µH
PVDD = 5.0V
10752-104
Figure 4. THD + N vs. Output Power into 4 Ω
100
10
1
0.1
0.01
0.001
0.001 1010.10.01
THD + N (%)
OUTPUT POWER (W)
PVDD = 2.5V
PVDD = 3.6V
R
L
= 3Ω + 7.5µH
PVDD = 5.0V
10752-105
Figure 5. THD + N vs. Output Power into 3 Ω
100
10
1
0.1
0.01
0.001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
R
L
= 8Ω + 33µH
250mW
500mW
1W
10752-106
Figure 6. THD + N vs. Frequency, PVDD = 5 V, R
L
= 8 Ω
100
10
1
0.1
0.01
0.001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
R
L
= 4Ω + 15µH
500mW
2W
1W
10752-107
Figure 7. THD + N vs. Frequency, PVDD = 5 V, R
L
= 4 Ω
100
10
1
0.1
0.01
0.001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
R
L
= 3Ω + 7.5µH
2.5W
2W
1W
10752-108
Figure 8. THD + N vs. Frequency, PVDD = 5 V, R
L
= 3 Ω
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

SSM4321ACBZ-R7

Mfr. #:
Buy SSM4321ACBZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Audio Amplifiers Mono 2.9W Class-D w/ Digital Crnt & Vout
Lifecycle:
New from this manufacturer.
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