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SSM4321ACBZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet SSM4321
Rev. 0 | Page 3 of 24
FUNCTIONAL BLOCK DIAGRAM
SENSE–
OUT+
OUT–
SENSE+
VREG IOVDD GND
GAIN
PVDD
IN+
IN–
SLOT
BCLK_TDM/PDM_CLK/LRCLK_I2S
FSYNC_TDM/BCLK_I2S
SDATAO/PDM_DATA
TDM
OUTPUT
PVDD
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
CLASS-D
MODULATOR
FULL-BRIDGE
POWER
STAGE
VOLTAGE
SENSE
CURRENT
SENSE
DIGITAL
DECIMATION
FILTERING
1.42V TO 3.6V 2.5V TO 5.5V
SSM4321
10752-001
Figure 1.
SSM4321 Data Sheet
Rev. 0 | Page 4 of 24
SPECIFICATIONS
PVDD = 5.0 V, IOVDD = 1.8 V, f
S
= 24 kHz with I
2
S output, T
A
= 25°C, R
L
= 8 Ω +33 µH, unless otherwise noted. For R
L
= 8 Ω, use a
200 mΩ V/I sense resistor; for R
L
= 4 Ω, use a 100 mΩ V/I sense resistor; for R
L
= 3 Ω, use a 75 mΩ V/I sense resistor.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power, RMS P
OUT
f = 1 kHz, 20 kHz bandwidth
R
L
= 8 Ω, THD = 1%, PVDD = 5.0 V 1.35 W
R
L
= 8 Ω, THD = 1%, PVDD = 3.6 V 0.70 W
R
L
= 8 Ω, THD = 1%, PVDD = 2.5 V 0.32 W
R
L
= 8 Ω, THD = 10%, PVDD = 5.0 V
1.70
R
L
= 8 Ω, THD = 10%, PVDD = 3.6 V 0.86 W
R
L
= 8 Ω, THD = 10%, PVDD = 2.5 V 0.4 W
R
L
= 4 Ω, THD = 1%, PVDD = 5.0 V 2.22 W
R
L
= 4 Ω, THD = 1%, PVDD = 3.6 V 1.12 W
R
L
= 4 Ω, THD = 1%, PVDD = 2.5 V 0.51 W
R
L
= 4 Ω, THD = 10%, PVDD = 5.0 V 2.8 W
R
L
= 4 Ω, THD = 10%, PVDD = 3.6 V 1.42 W
R
L
= 4 Ω, THD = 10%, PVDD = 2.5 V 0.64 W
R
L
= 3 Ω, THD = 1%, PVDD = 5.0 V 3.00 W
R
L
= 3 Ω, THD = 1%, PVDD = 3.6 V 1.51 W
R
L
= 3 Ω, THD = 1%, PVDD = 2.5 V 0.68 W
R
L
= 3 Ω, THD = 10%, PVDD = 5.0 V 3.77 W
R
L
= 3 Ω, THD = 10%, PVDD = 3.6 V 1.90 W
R
L
= 3 Ω, THD = 10%, PVDD = 2.5 V 0.86 W
Efficiency η P
OUT
= 1.4 W into 8 Ω, PVDD = 5.0 V 89 %
P
OUT
= 2.8 W into 3 Ω, PVDD = 5.0 V 82 %
Total Harmonic Distortion
Plus Noise
THD + N
P
OUT
= 1 W into 8 Ω, f = 1 kHz,
PVDD = 5.0 V
0.01
P
OUT
= 0.5 W into 8 Ω, f = 1 kHz,
PVDD = 3.6 V
0.01 %
Input Common-Mode Voltage
Range
V
CM
1.0 PVDD − 1 V
Common-Mode Rejection Ratio CMRR
GSM
V
CM
= 100 mV rms at 1 kHz 50 dB
Average Switching Frequency f
SW
256 kHz
Clock Frequency f
OSC
6.2 MHz
Differential Output Offset Voltage V
OOS
Gain = 6 dB 0.3 5.0 mV
POWER SUPPLY
Supply Voltage Range PVDD Guaranteed from PSRR test 2.5 5.5 V
IOVDD 1.42 3.6 V
Power Supply Rejection Ratio PSRR
GSM
V
RIPPLE
= 100 mV at 217 Hz, inputs are
ac-grounded, C
IN
= 0.1 µF
86 dB
Supply Current, PVDD I
SYPVDD
V
IN
= 0 V
No load, PVDD = 5.0 V 3.7 mA
No load, PVDD = 3.6 V 3.1 mA
No load, PVDD = 2.5 V 2.9 mA
R
L
= 8 Ω, PVDD = 5.0 V 3.8 mA
R
L
= 8 Ω, PVDD = 3.6 V
3.2
R
L
= 8 Ω, PVDD = 2.5 V 2.9 mA
Supply Current, IOVDD I
SYIOVDD
IOVDD = 1.8 V 0.41 mA
Shutdown Current, PVDD I
SDPVDD
No BCLK, PVDD = 5.0 V 0.1 µA
Shutdown Current, IOVDD I
SDIOVDD
No BCLK, IOVDD = 1.8 V 0.77 µA
Data Sheet SSM4321
Rev. 0 | Page 5 of 24
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GAIN CONTROL
Closed-Loop Gain Gain 0 12 dB
Input Impedance Z
IN
BCLK enabled, fixed input impedance
(0 dB to 12 dB)
80 kΩ
SHUTDOWN CONTROL
Turn-On Time t
WU
From BCLK start 12.5 ms
Turn-Off Time t
SD
From BCLK removal 5 µs
Output Impedance
Z
OUT
No BCLK
>100
AMPLIFIER NOISE PERFORMANCE
Output Voltage Noise e
n
f = 20 Hz to 20 kHz, inputs are
ac-grounded, gain = 6 dB, A-weighted
PVDD = 5.0 V 30 µV
PVDD = 3.6 V 30 µV
Signal-to-Noise Ratio SNR P
OUT
= 1.3 W, R
L
= 8 Ω, A-weighted 101 dB
OUTPUT SENSING
Output Sampling Rate, TDM f
S
LRCLK/FSYNC pulse rate 8 48 kHz
BCLK Frequency, TDM f
BCLK
1 to 4 slots used 0.512 6.144 MHz
Voltage Sense Signal-to-Noise
Ratio
SNRV A-weighted 77 dB
Voltage Sense Full-Scale Output
Voltage
V
FS
Amplifier voltage with 0 dBFS ADC
output
6 V
P
Voltage Sense Absolute Accuracy 1.5 %
Voltage Sense Gain Drift T
A
= 10°C to 60°C 1 %
Current Sense Signal-to-Noise
Ratio
SNRI A-weighted 72 dB
Current Sense Full-Scale Input
Voltage
V
IS
I
SENSE
converter voltage with 0 dBFS ADC
output
0.150 V
P
Current Sense Absolute Accuracy 3 %
Current Sense Gain Drift T
A
= 10°C to 60°C, ideal R
SENSE
1 %
PVDD Sense Full-Scale Range PV
FS
PVDD with full-scale ADC output 2 6 V
PVDD Sense Absolute Accuracy 3 %
Current and Voltage Sense
Linearity
From −80 dBr to 0 dBr 1 dB
ADC −3 dB Corner Frequency f
C
Digital high-pass filter
Output f
S
= 48 kHz 3.75 Hz
Output f
S
= 24 kHz
1.875
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
BCLK, FSYNC PINS Ball D2 and Ball D3
Input Voltage High
V
IH
0.7 × IOVDD
3.6
Input Voltage Low V
IL
−0.3 0.3 × IOVDD V
Input Leakage Current High I
IH
1 µA
Input Leakage Current Low I
IL
1 µA
Input Capacitance C
IN
5 pF
SDATAO/PDM_DATA PIN Ball D1
Output Drive Strength IOVDD = 1.5 V 3.5 mA
IOVDD = 1.8 V 4.5 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

SSM4321ACBZ-R7

Mfr. #:
Buy SSM4321ACBZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Audio Amplifiers Mono 2.9W Class-D w/ Digital Crnt & Vout
Lifecycle:
New from this manufacturer.
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