PX1011B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 27 June 2011 16 of 32
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
8.10.1 8b/10b decode errors
For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the
data stream in place of the bad byte, and encodes RXSTATUS with a decode error during
the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 11
the receiver is receiving a stream of bytes Rx-a through Rx-z, and byte Rx-c has
an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel
interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that
cannot be decoded may also have bad disparity, but the 8b/10b error has precedence.
8.10.2 Disparity errors
For a detected disparity error, the PHY asserts RXSTATUS with the disparity error code
during the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 12
the receiver detected a disparity error on Rx-c data byte, and indicates this with
the assertion of RXSTATUS.
8.10.3 Elastic buffer
For elastic buffer errors, an underflow is signaled during the clock cycle when the spurious
symbol is moved across the parallel interface. The symbol moved across the interface is
the EDB symbol. In the timing diagram Figure 13
, the PHY is receiving a repeating set of
symbols Rx-a through Rx-z. The elastic buffer underflow causing the EDB symbol to be
inserted between the Rx-c and Rx-d symbols. The PHY drives RXSTATUS to indicate
buffer underflow during the clock cycle when the EDB is presented on the parallel
interface.
Fig 11. 8b/10b decode errors
001aac780
RXCLK
Rx-a Rx-b EDB
000b 100b 000b
Rx-d Rx-e
RXVALID
RXDATA[7:0]
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
Fig 12. Disparity errors
001aac781
RXCLK
Rx-a Rx-b Rx-c
000b 111b 000b
Rx-d Rx-e
RXVALID
RXDATA[7:0]
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
