PX1011B-EL1/G,557 Datasheet PX1011B-EL1/N,551, PX1011B-EL1/N,557, PX1011BI-EL1/G,557 | P7-P9

Product data sheet Rev. 6 — 27 June 2011 7 of 32

NXP Semiconductors

PX1011B

PCI Express stand-alone X1 PHY

Table 9. PXPIPE interface status signals

Symbol Pin Type Signaling Description

RXVALID C8 output SSTL_2 indicates symbol lock and valid data on

RX_DATA and RX_DATAK

PHYSTATUS D8 output SSTL_2 used to communicate completion of several PHY

functions including power management state

transitions and receiver detection

RXIDLE A2 output SSTL_2 indicates receiver detection of an electrical idle;

this is an asynchronous signal

RXSTATUS0 A9 output SSTL_2 encodes receiver status and error codes for the

received data stream and receiver detection (see

Table 15

)

RXSTATUS1 B9 output SSTL_2

RXSTATUS2 C9 output SSTL_2

Table 10. Clock and reference signals

Symbol Pin Type Signaling Description

TXCLK J8 input SSTL_2 source synchronous 250 MHz transmit clock

input from MAC. All input data and signals to the

PHY are synchronized to this clock.

RXCLK A8 output SSTL_2 source synchronous 250 MHz clock output for

received data and status signals bound for the

MAC.

REFCLK_P B1 input PCIe I/O 100 MHz reference clock input. This is the

spread spectrum source clock for PCI Express.

Differential pair input with 50  on-chip

termination.

REFCLK_N C1 input PCIe I/O

PVT D6 - analog I/O input or output to create a compensation signal

internally that will adjust the I/O pads

characteristics as PVT drifts. Connect to V

through a 49.9  resistor.

VREFS J2 input reference voltage input for SSTL_2 class I

signaling. Connect to 1.25 V.

Table 11. 3.3 V JTAG signals

Symbol Pin Type Signaling Description

TMS E4 input 3.3 V CMOS test mode select input

TRST_N F4 input 3.3 V CMOS test reset input for the JTAG interface;

active LOW

TCK F3 input 3.3 V CMOS test clock input for the JTAG interface

TDI G3 input 3.3 V CMOS test data input

TDO H3 output 3.3 V CMOS test data output

Product data sheet Rev. 6 — 27 June 2011 8 of 32

NXP Semiconductors

PX1011B

PCI Express stand-alone X1 PHY

8. Functional description

The main function of the PHY is to convert digital data into electrical signals and vice

versa. The PCI Express PHY handles the low level PCI Express protocol and signaling.

The PX1011B PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a

Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY

handles the low level PCI Express protocol and signaling. This includes features such as

Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding,

analog buffers, elastic buffer and receiver detection.

The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface

for the PCI Express (PIPE) specification. The following feature have been added:

• Source synchronous clocks for RX and TX data to simplify timing closure.

The 8-bit data width PXPIPE interface operates at 250 MHz with SSTL_2 class I

signaling. PX1011B does not integrate SSTL_2 termination resistors inside the IC.

The PCI Express link consists of a differential input pair and a differential output pair. The

data rate of these signals is 2.5 Gbit/s.

8.1 Receiving data

Incoming data enters the chip at the RX interface. The receiver converts these signals

from small amplitude differential signals into rail-to-rail digital signals. The carrier detect

circuit detects whether data is present on the line and passes this information through to

the SerDes and PCS.

If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers

the clock from the data and then uses this clock for re-timing the data (i.e., recovering the

data).

Table 12. PCI Express PHY power supplies

Symbol Pin Type Signaling Description

DDA1

D5 power 1.2 V analog power supply for serializer and

de-serializer

DDA2

D4 power 3.3 V analog power supply for serializer and

de-serializer

DDD1

E3, E5 power 3.3 V power supply for JTAG I/O

DDD2

C3, C5, C7, E7,

G5, G7

power 2.5 V power supply for SSTL_2 I/O

DDD3

E6, F5, F6 power 1.2 V power supply for core

D3 power 1.2 V power supply for high-speed serial

PCI Express I/O pads and PVT

A1, B2, B5, B8,

C2, C4, C6, D1,

D2, D7, E2, E8,

F2, F7, G1, G2,

G4, G6, H2, H5,

ground ground

Product data sheet Rev. 6 — 27 June 2011 9 of 32

NXP Semiconductors

PX1011B

PCI Express stand-alone X1 PHY

The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits

parallel data.

Since the S2P has no knowledge about the data, the word alignment is still random. This

is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character

(K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw

data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the

resulting data to the right clock domain, which is the RX source synchronous clock

domain.

8.2 Transmitting data

When the PHY transmits, it receives 8-bit data from the MAC. This data is encoded using

an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures the

serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density for

clock recovery at the receiver side.

The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial

data streams. These data streams are latched into the transmitter, where they are

converted into small amplitude differential signals. The transmitter has built-in

de-emphasis for a larger eye opening at the receiver side.

The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a

30 kHz to 33 kHz spread spectrum.

8.3 Clocking

There are three clock signals used by the PX1011B:

• REFCLK is a 100 MHz external reference clock that the PHY uses to generate the

250 MHz data clock and the internal bit rate clock. This clock may have

30 kHz to 33 kHz spread spectrum modulation.

• TXCLK is a reference clock that the PHY uses to clock the TXDATA and command.

This source synchronous clock is provided by the MAC. The PHY expects that the

rising edge of TXCLK is centered to the data. The TXCLK has to be synchronous with

RXCLK.

• RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status

signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to the

center of the data. RXCLK may be used by the MAC to clock its internal logic.

8.4 Reset

The PHY must be held in reset until power and REFCLK are stable. It takes the PHY

64 s maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK

frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal

clocks are stable.

The PIPE specification recommends that while RESET_N is asserted, the MAC should

have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL

de-asserted and power state P1. The MAC can also assert a reset if it receives a physical

layer reset packet.

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PX1011B-EL1/G,557

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