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PX1011B-EL1/G,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PX1011B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 27 June 2011 19 of 32
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
9. Limiting values
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3.1-1999, standard for ESD sensitivity testing, Charged Device
Model - component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Thermal characteristics
[1] Significant variations can be expected due to system variables, such as adjacent devices, or actual air flow
across the package.
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DDD1
digital supply voltage 1 for JTAG I/O 0.5 +4.6 V
V
DDD2
digital supply voltage 2 for SSTL_2 I/O 0.5 +3.75 V
V
DDD3
digital supply voltage 3 for core 0.5 +1.7 V
V
DD
supply voltage for high-speed
serial I/O and PVT
0.5 +1.7 V
V
DDA1
analog supply voltage 1 for serializer 0.5 +1.7 V
V
DDA2
analog supply voltage 2 for serializer 0.5 +4.6 V
V
ESD
electrostatic discharge voltage HBM
[1]
- 2000 V
CDM
[2]
-500V
T
stg
storage temperature 55 +150 C
T
j
junction temperature 55 +125 C
T
amb
ambient temperature operating
commercial 0 +70 C
industrial 40 +85 C
Table 17. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient in free air
[1]
44 K/W
R
th(j-c)
thermal resistance from junction to case in free air
[1]
10 K/W
PX1011B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 27 June 2011 20 of 32
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
11. Characteristics
Table 18. PCI Express PHY characteristics
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DDD1
digital supply voltage 1 for JTAG I/O 3.0 3.3 3.6 V
V
DDD2
digital supply voltage 2 for SSTL_2 I/O 2.3 2.5 2.7 V
V
DDD3
digital supply voltage 3 for core 1.15 1.2 1.3 V
V
DD
supply voltage for high-speed serial I/O
and PVT
1.15 1.2 1.3 V
V
DDA1
analog supply voltage 1 for serializer 1.15 1.2 1.3 V
V
DDA2
analog supply voltage 2 for serializer 3.0 3.3 3.6 V
I
DDD1
digital supply current 1 for JTAG I/O 0.1 1 2 mA
I
DDD2
digital supply current 2 for SSTL_2; no load - 24 35 mA
I
DDD3
digital supply current 3 for core 5 10 15 mA
I
DD
supply current for high-speed serial I/O
and PVT
15 20 30 mA
I
DDA1
analog supply current 1 for serializer 15 20 31 mA
I
DDA2
analog supply current 2 for serializer 7 10 15 mA
Receiver
UI unit interval 399.88 400 400.12 ps
V
RX_DIFFp-p
differential input peak-to-peak voltage 0.205 - 1.2 V
t
RX_MAX_JITTER
maximum receiver jitter time - - 0.6 UI
V
IDLE_DET_DIFFp-p
electrical idle detect threshold 65 - 205 mV
Z
RX_DC
DC input impedance 40 50 60
Z
RX_HIGH_IMP_DC
powered-down DC input impedance 200 - - k
RL
RX_DIFF
differential return loss 15 - - dB
RL
RX_CM
common mode return loss 6 - - dB
t
lock(CDR)(ref)
CDR lock time (reference loop) - - 50 s
t
lock(CDR)(data)
CDR lock time (data loop) - - 2.5 s
t
RX_latency
receiver latency 1 clock cycle is 4 ns 6 - 13 clock
cycle
Reference clock
f
clk(ref)
reference clock frequency 99.97 100 100.03 MHz
f
mod(clk)(ref)
reference clock modulation frequency
range
0.5 - +0 %
f
mod(clk)(ref)
reference clock modulation frequency 30 - 33 kHz
V
IH(se)REFCLK
REFCLK single-end HIGH-level input
voltage
- 0.7 1.15 V
V
IL(se)REFCLK
REFCLK single-end LOW-level input
voltage
0.3 0 - V
Z
C-DC
clock source DC impedance 40 50 60
PX1011B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 27 June 2011 21 of 32
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
dV/dt rate of change of voltage at rising edge;
measured from 150 mV
to +150 mV on the
differential waveform;
Figure 17
0.6 - 4.0 V/ns
at falling edge;
measured from +150 mV
to 150 mV on the
differential waveform;
Figure 17
0.6 - 4.0 V/ns
V
IH
differential input HIGH voltage +150 - - mV
V
IL
differential input LOW voltage - - 150 mV
REFCLK
duty cycle on pin REFCLK on pin REFCLK_N and
pin REFCLK_P
40 - 60 %
Transmitter
UI unit interval 399.88 400 400.12 ps
V
TX_DIFFp-p
differential peak-to-peak output
voltage
0.8 - 1.2 V
t
TX_EYE_m-mJITTER
maximum time between the jitter
median and maximum deviation from
the median
-3550ps
t
TX_JITTER_MAX
maximum transmitter jitter time - 60 100 ps
V
TX_DE_RATIO
de-emphasized differential output
voltage ratio
3.0 - 4.0 dB
t
TX_RISE
D+/D TX output rise time 50 75 - ps
t
TX_FALL
D+/D TX output fall time 50 75 - ps
V
TX_CM_ACp
RMS AC peak common mode output
voltage
--20mV
V
CM_DC_ACT_IDLE
absolute delta of DC common mode
voltage during L0 and electrical idle
0- 100mV
V
CM_DC_LINE
absolute delta of DC common mode
voltage between D+ and D
0- 25mV
V
TX_CM_DC
TX DC common mode voltage 0 - 3.6 V
I
TX_SHORT
TX short-circuit current limit - 20 90 mA
RL
TX_DIFF
differential return loss 12 - - dB
RL
TX_CM
common mode return loss 6 - - dB
Z
TX_DC
transmitter DC impedance 40 50 60
C
TX
AC coupling capacitor 75 100 200 nF
t
lock(PLL)
PLL lock time - - 50 s
t
TX_latency
transmitter latency 1 clock cycle is 4 ns 4 - 9 clock
cycle
t
P0s_exit_latency
P0s state exit latency - - 2.5 s
t
P1_exit_latency
P1 state exit latency - - 64 s
t
RESET-PHYSTATUS
RESET_N HIGH to PHYSTATUS LOW
time
--64s
Table 18. PCI Express PHY characteristics
…continued
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PX1011B-EL1/G,557

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Manufacturer:
NXP Semiconductors
Description:
PCI Interface IC PCI EXPRESS STAND
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