Document Number: 002-10221 Rev. *B Page 11 of 17
AC Switching Characteristics
Over the Operating Range
Parameter
[6]
Alt.
Parameter
Description Min Max Min Max Min Max Unit
f
SCL
[7]
SCL clock frequency – 0.1 – 0.4 – 1.0 MHz
t
SU; STA
Start condition setup for repeated Start 4.7 – 0.6 – 0.25 – s
t
HD;STA
Start condition hold time 4.0 – 0.6 – 0.25 – s
t
LOW
Clock LOW period 4.7 – 1.3 – 0.6 – s
t
HIGH
Clock HIGH period 4.0 – 0.6 – 0.4 – s
t
SU;DAT
t
SU;DATA
Data in setup 250 – 100 – 100 – ns
t
HD;DAT
t
HD;DATA
Data in hold 0 – 0 – 0 – ns
t
DH
Data output hold (from SCL @ V
IL
) 0 – 0 – 0 – ns
t
R
[8]
t
r
Input rise time – 1000 – 300 – 300 ns
t
F
[8]
t
f
Input fall time – 300 – 300 – 100 ns
t
SU;STO
STOP condition setup 4.0 – 0.6 – 0.25 – s
t
AA
t
VD;DATA
SCL LOW to SDA Data Out Valid – 3 – 0.9 – 0.55 s
t
BUF
Bus free before new transmission 4.7 – 1.3 – 0.5 – s
t
SP
Noise suppression time constant on SCL, SDA – 50 – 50 – 50 ns
Figure 13. Read Bus Timing Diagram
Figure 14. Write Bus Timing Diagram
t
SU:STA
Start
t
R
t
F
Stop Start
t
BUF
t
HIGH
1/fSCL
t
LOW
t
SP
t
SP
Acknowledge
t
HD:DAT
t
SU:DAT
t
AA
t
DH
SCL
SDA
t
SU:STO
Start
Stop Start Acknowledge
t
AA
t
HD:DAT
t
HD:STA
SCL
SDA
t
SU:DAT
Notes
6. Test conditions assume signal transition time of 10 ns or less, timing reference levels of V
DD
/2, input pulse levels of 0 to V
DD
(typ), and output loading of the specified
I
OL
and load capacitance shown in Figure 12.
7. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to f
SCL
(max).
8. These parameters are guaranteed by design and are not tested.
