ISL6263CRZ Datasheet ISL6263CRZ-T, ISL6263CRZ | P16-P18

FN9213.2

June 10, 2010

To see whether the NTC network successfully compensates

the DCR change over temperature, one can apply full load

current and wait for the thermal steady state and see how

much the output voltage deviates from the initial voltage

reading. A good compensation can limit the drift to less than

2mV. If the output voltage is decreasing when the temperature

increases, that ratio between the NTC thermistor value and

the rest of the resistor divider network has to be increased.

Following the evaluation board value and layout of NTC

placement will minimize the engineering time.

The current sensing traces should be routed directly to the

inductor pads for accurate DCR voltage drop measurement.

However, due to layout imperfection, the calculated R

DRP2

may still need slight adjustment to achieve optimum load line

slope. It is recommended to adjust R

DRP2

after the system

has achieved thermal equilibrium at full load. For example, if

the maximum load current is 20A, one should apply a 20A

load current and look for 160mV output voltage droop. If the

voltage droop is 155mV, the new value of R

DRP2

calculated by Equation 16:

For the best accuracy, the effective resistance on the DFB

and VSUM pins should be identical so that the bias current

of the droop amplifier does not cause an offset voltage.

Dynamic Droop Capacitor Design Using DCR

Sensing

Figure 10 shows the desired waveforms during load

transient response. V

CCGFX

needs to follow the change in

core

as close as possible. The transient response of

CCGFX

is determined by several factors, namely the choice

of output inductor, output capacitor, compensator design,

and the design of droop capacitor C

If C

is designed correctly, the voltage V

DROOP

-V

will be

an excellent representation of the inductor current. Given the

correct C

design, V

CCGFX

has the best chance of tracking

CORE

, if not, its voltage will be distorted from the actual

waveform of the inductor current and worsens the transient

response. Figure 11 shows the transient response when C

is too small allowing V

CCGFX

to sag excessively during the

load transient. Figure 12 shows the transient response when

is too large. V

CCGFX

takes too long to droop to its final

value.

The current sensing network consists of R

NTCEQ

, R

, and

. The effective resistance is the parallel of R

NTCEQ

and

. The RC time constant of the current sensing network

needs to match the L/DCR time constant of the inductor to

get the correct representation of the inductor current

waveform. Equation 17 shows this relationship:

Solution of C

yields Equation 18:

For example: L = 0.45µH, DCR = 1.1mΩ, R

= 7.68kΩ, and

NTCEQ

= 3.4kΩ:

Since the inductance and the DCR typically have 20% and

7% tolerance respectively, C

needs to be fine tuned on the

DRP2new

160mV

155mV

-------------------

DRP1

DPR2

–()R

DRP1

–⋅=

(EQ. 16)

core

droop

FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE

WAVEFORMS

core

FIGURE 11. LOAD TRANSIENT RESPONSE WHEN C

IS TOO

SMALL

core

FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C

IS TOO

LARGE

DCR

-------------

NTCEQ

⋅

NTCEQ

-------------------------------------- -

⎝⎠

⎜⎟

⎛⎞

⋅=

(EQ. 17)

DCR

-------------

⎝⎠

⎛⎞

NTCEQ

⋅

NTCEQ

-------------------------------------- -

⎝⎠

⎜⎟

⎛⎞

--------------------------------------------

(EQ. 18)

0.45μH

1.1mΩ

--------------------

⎝⎠

⎛⎞

3.4kΩ 7.68kΩ⋅

3.4kΩ 7.68kΩ+

-------------------------------------------

⎝⎠

⎛⎞

-------------------------------------------------

174nF==

(EQ. 19)

ISL6263

FN9213.2

June 10, 2010

actual board by examining the transient voltage. It is

recommended to choose the minimum capacitance based

on the maximum inductance. C

also needs to be a high-

grade capacitor such as NPO/COG or X7R with tight

tolerance. The NPO/COG caps are only available in small

capacitance values. In order to use such capacitors, the

resistors and thermistors surrounding the droop voltage

sensing and droop amplifier need to be scaled up 10x to

reduce the capacitance by 10x.

Static and Dynamic Droop using Discrete Resistor

Sensing

Figure 3 shows a detailed schematic using discrete resistor

sensing of the inductor current. Figure 9 shows the

equivalent circuit. Since the current sensing resistor voltage

represents the actual inductor current information, R

and

simply provide noise filtering. A low ESL sensing resistor

is strongly recommended for R

SNS

because this parameter

is the most significant source of noise that affects discrete

resistor sensing. It is recommended to start out using 100Ω

for R

and 47pF for C

. Since the current sensing

resistance changes very little with temperature, the NTC

network is not needed for thermal compensation. Discrete

resistor sensing droop design follows the same approach as

DCR sensing. The voltage on the current sensing resistor is

given by Equation 20:

Equation 21 shows the droop amplifier gain. So the actual

droop is given by:

Solution to R

DRP2

yields Equation 22:

For example: R

droop

= 8.0mΩ, R

SNS

= 1.0mΩ, and

DRP1

=1kΩ, R

DRP2

then = 7kΩ.

The current sensing traces should be routed directly to the

current sensing resistor pads for accurate measurement.

However, due to layout imperfection, the calculated R

DRP2

may still need slight adjustment to achieve optimum load line

slope. It is recommended to adjust R

DRP2

after the system

has achieved thermal equilibrium at full load.

Dynamic Mode of Operation - Compensation

Parameters

The voltage regulator is equivalent to a voltage source in

series with the output impedance. The voltage source is the

VID state and the output impedance is 8.0mΩ in order to

achieve the 8.0mV/A load line. It is highly recommended to

design the compensation such that the regulator output

impedance is 8.0mΩ. Intersil provides a spreadsheet to

calculate the compensator parameters. Caution needs to be

used in choosing the input resistor to the FB pin. Excessively

high resistance will cause an error to the output voltage

regulation due to the bias current flowing through the FB pin.

It is recommended to keep this resistor below 3kΩ.

Layout Considerations

As a general rule, power should be on the bottom layer of

the PCB and weak analog or logic signals are on the top

layer of the PCB. The ground-plane layer should be adjacent

to the top layer to provide shielding.

Inductor Current Sensing and the NTC Placement

It is crucial that the inductor current be sensed directly at the

PCB pads of the sense element, be it DCR sensed or

discrete resistor sensed. The effect of the NTC on the

inductor DCR thermal drift is directly proportional to its

thermal coupling with the inductor and thus, the physical

proximity to it.

Signal Ground and Power Ground

The ground plane layer should have a single point

connection to the analog ground at the VSS pin. The VSS

island should be located under the IC package along with

the weak analog traces and components. The paddle on the

bottom of the ISL6263 QFN package is not electrically

connected to the IC however, it is recommended to make a

good thermal connection to the VSS island using several

vias. Connect the input capacitors, the output capacitors,

and the source of the lower MOSFETs to the power ground

plane.

LGATE, PVCC, and PGND

PGND is the return path for the pull-down of the LGATE

low-side MOSFET gate driver. Ideally, PGND should be

connected to the source of the low-side MOSFET with a

low-resistance, low-inductance path. The LGATE trace

should be routed in parallel with the trace from the PGND

pin. These two traces should be short, wide, and away from

other traces because of the high peak current and extremely

fast dv/dt. PVCC should be decoupled to PGND with a

ceramic capacitor physically located as close as practical to

the IC pins.

RSNS

SNS

⋅=

(EQ. 20)

droop

SNS

DRP2

DRP1

-------------------

⎝⎠

⎜⎟

⎛⎞

⋅=

(EQ. 21)

DRP2

DRP1

droop

SNS

-------------------

1–

⎝⎠

⎜⎟

⎛⎞

⋅=

(EQ. 22)

INDUCTOR

VIAS TO

GROUND

PLANE

VIN

VOUT

PHASE

NODE

GND

OUTPUT

CAPACITORS

LOW-SIDE

MOSFETS

INPUT

CAPACITORS

SCHOTTKY

DIODE

HIGH-SIDE

MOSFETS

FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT

ISL6263

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FN9213.2

June 10, 2010

UGATE, BOOT, and PHASE

PHASE is the return path for the entire UGATE high-side

MOSFET gate driver. The layout for these signals require

similar treatment, but to a greater extent, than those for

LGATE, PVCC, and PGND. These signals swing from

approximately VIN to VSS and are more likely to couple into

other signals.

VSEN and RTN

These traces should be laid out as noise sensitive. For

optimum load line regulation performance, the traces

connecting these two pins to the Kelvin sense leads of the

processor should be laid out away from rapidly rising voltage

nodes, (switching nodes) and other noisy traces. The filter

capacitors C

FILTER1

, C

FILTER2

, and C

FILTER3

used in

conjunction with filter resistors R

FILTER1

and R

FILTER2

form

common mode and differential mode filters as shown in

Figure 8. The noise environment of the application and

actual board layout conditions will drive the extent of filter

complexity. The maximum recommended resistance for

FILTER1

and R

FILTER2

is approximately 10Ω to avoid

interaction with the 50kΩ input resistance of the remote

sense differential amplifier. The physical location of these

resistors is not as critical as the filter capacitors. Typical

capacitance values for C

FILTER1

, C

FILTER2

, and C

FILTER3

range between 330pF to 1000pF and should be placed near

the IC.

RBIAS and I2UA

The resistors R

RBIAS

and R

I2UA

should be placed in close

proximity to the ISL6263 using a noise-free current return

path to the VSS pin.

SOFT, OCSET, V W, COMP, FB, VDIFF, DROOP,

DFB, VO, and VSUM

The traces and components associated with these pins

require close proximity to the IC as well as close proximity to

each other. This section of the converter circuit needs to be

located above the island of analog ground with the

single-point connection to the VSS pin.

Resistor R

is preferably located near the boundary

between the power ground and the island of analog ground

connected to the VSS pin.

VID<0:4>, AF_EN, PGOOD, and VR_ON

These are logic signals that do not require special attention.

FDE

This logic signal should be treated as noise sensitive and

should be routed away from rapidly rising voltage nodes,

(switching nodes) and other noisy traces.

VIN

The VIN signal should be connected near the drain of the

high-side MOSFET.

Copper Size for the Phase Node

The parasitic capacitance and parasitic inductance of the

phase node should be kept very low to minimize ringing. It is

best to limit the size of the PHASE node copper in strict

accordance with the current and thermal management of the

application. An MLCC should be connected directly across

the drain of the high-side MOSFET and the source of the

low-side MOSFET to suppress turn-off voltage spikes.

ISL6263

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ISL6263CRZ

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Voltage Regulators - Switching Regulators 1 PHS INT DC/DC BUCK CNTRLR FOR INTEL

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ISL6263CRZ

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