4
FN9213.2
June 10, 2010
Simplified Application Circuit for DCR Current Sensing
VDD PVCC
DROOP
VSS
VW
RTN
COMP
FB
VIN
PHASE
BOOT
UGATE
LGATE
PGND
C
OUT
L
OUT
ISL6263
Q
HS
C
BOOT
C
IN
V
CCGFX
Q
LS
RBIAS
SOFT
I2UA
VSUM
OCSET
VO
DFB
AF_EN
VR_ON
VID<0:4>
PGOOD
FDE
VDIFF
V
5V
V
CC_SNS
V
SS_SNS
VSEN
C
SOFT
R
VDD
R
RBIAS
C
VDD
R
COMP
C
DRP
R
OCSET
R
FSET
C
FSET
R
DIFF1
R
S
R
DRP1
R
DRP2
C
COMP1
C
DIFF
C
N
R
NTCP
C
COMP2
R
DIFF2
V
IN
FIGURE 2. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSING
R
I2UA
C
PVCC
R
GND
R
NTCS
R
NTC
0
ISL6263
5
FN9213.2
June 10, 2010
Simplified Application Circuit for Resistive Current Sensing
FIGURE 3. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH RESISTIVE CURRENT SENSING
VDD PVCC
DROOP
VSS
VW
RTN
COMP
FB
PHASE
BOOT
UGATE
LGATE
PGND
C
OUT
L
OUT
ISL6263
Q
HS
C
BOOT
C
IN
V
CCGFX
Q
LS
RBIAS
SOFT
I2UA
VSUM
OCSET
VO
DFB
AF_EN
VR_ON
VID<0:4>
PGOOD
FDE
VDIFF
V
5V
V
CC_SNS
V
SS_SNS
VIN
VSEN
C
SOFT
R
VDD
R
RBIAS
C
VDD
R
COMP
C
DRP
R
OCSET
R
FSET
C
FSET
R
DIFF1
R
S
R
DRP1
R
DRP2
C
COMP1
C
DIFF
C
N
C
COMP2
R
DIFF2
V
IN
R
SNS
R
I2UA
C
PVCC
R
GND
0
ISL6263
6
FN9213.2
June 10, 2010
Absolute Voltage Ratings
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10µJ) -5.0V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) -4.0V
LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) -2.0V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) θ
JA
(°C/W) θ
JC
(°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . . 35 6
Junction Temperature Range. . . . . . . . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . -10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . -10°C to 100°C
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications These specifications apply for T
A
= -10°C to +100°C, unless otherwise stated. All typical specifications
T
A
= +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
VIN
VIN Input Resistance R
VIN
VR_ON = 3.3V - 1.0 - MΩ
VIN Shutdown Current I
VIN_SHDN
VR_ON = 0V, VIN = 25V - - 1.0 µA
VDD and PVCC
VDD Input Bias Current I
VDD
VR_ON = 3.3V - 2.4 3.0 mA
VDD Shutdown Current I
VDD_SHDN
VR_ON = 0V, VDD = 5.0V - - 1.0 µA
VDD POR THRESHOLD
Rising VDD POR Threshold Voltage
V
VDD_THR
-4.354.50 V
Falling VDD POR Threshold Voltage
V
VDD_THF
3.85 4.10 - V
REGULATION
Output Voltage Range
V
GFX_MAX
VID<4:0> = 00000 - 1.28750 - V
V
GFX_MIN
VID<4:0> = 11111 - 0.41200 - V
VID Voltage Step VID<4:0> = 00000 to 11110 (1.28750V to
0.51500V)
- 25.75 - mV/step
VID<4:0> = 11110 to 11111 (0.51500V to
0.41200V)
- 103 - mV
System Accuracy VID = 1.28750V to 0.74675V
T
A
= 0°C to +100°C
-0.5 - 0.5 %
VID = 0.72100V to 0.51500V
T
A
= 0°C to +100°C
-1.0 - 1.0 %
VID = 0.41200
T
A
= 0°C to +100°C
-2.0 - 2.0 %
PWM
Nominal Frequency
F
SW
R
FSET
= 7kΩ, V
COMP
= 2V 318 333 348 kHz
ISL6263

ISL6263CRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Voltage Regulators - Switching Regulators 1 PHS INT DC/DC BUCK CNTRLR FOR INTEL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet