R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 14 of 45
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Table 1.7 Pin Name Information by Pin Number of PWQN0028KA-B Package
Pin
Number
Control
Pin
Port
I/O Pin Functions for Peripheral Modules
Interrupt Timer
Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I
2
C bus
Interface
A/D
Converter
1NC
2XOUTP4_7
3 VSS/AVSS
4NC
5NC
6XINP4_6
7NC
8VCC/AVCC
9MODE
10 P4_5
INT0
RXD1
11 P1_7
INT10
CNTR00
12 P1_6 CLK0 SSI01
13 P1_5
INT11
CNTR01 RXD0
14 P1_4 TXD0
15 NC
16 P1_3
KI3
TZOUT AN11
17 P1_2
KI2
CMP0_2 AN10
18 NC
19 NC
20 VREF P4_2
21 NC
22 P1_1
KI1
CMP0_1 AN9
23 P1_0
KI0
CMP0_0 AN8
24 P3_3
INT3
TCIN/CMP1_0 SSI00
25 P3_4 CMP1_1
SCS
SDA
26 P3_5 CMP1_2 SSCK SCL
27 P3_7
CNTR0
TXD1 SSO
28
RESET
R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 15 of 45
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two sets of register bank.
Figure 2.1 CPU Register
R2
b31
b15 b8b7
b0
Data registers
(1)
Address registers
(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19
b0
INTBL
FB
Frame base register
(1)
The 4 high order bits of INTB are INTBH and
the 16 low bits of INTB are INTBL.
Interrupt table register
b19
b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL
DZSBOIU
b15
b0
b15
b0
b15
b0
b8
b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 16 of 45
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0
can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data
registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-
bit data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
It is also used for transfer and arithmetic and logic operations. A1 is analogous to A0. A1 can be
combined with A0 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and
logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.

R5F211A2DSP#U0

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 8K I-Temp Pb-Free 20-SSOP
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New from this manufacturer.
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