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R5F211A2DSP#U0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 29 of 45
REJ03B0144-0140
NOTES:
1. This condition is not applicable when using with Vcc ≥ 1.0 V.
2. When turning power on after the time to hold the external power below effective voltage (V
por1) exceeds10 s, refer to Table
5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset).
3. t
w(por2) is the time to hold the external power below effective voltage (Vpor2).
NOTES:
1. When not using voltage monitor 1, use with Vcc≥ 2.7 V.
2. t
w(por1) is the time to hold the external power below effective voltage (Vpor1).
Figure 5.3 Reset Circuit Electrical Characteristics
Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
V
por2 Power-on reset valid voltage -20°C ≤ Topr ≤ 85°C −−Vdet1 V
t
w(Vpor2-Vdet1) Supply voltage rising time when power-on reset is
deasserted
(1)
-20°C ≤ Topr ≤ 85°C,
t
w(por2) ≥ 0s
(3)
−−100 ms
Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
V
por1 Power-on reset valid voltage -20°C ≤ Topr ≤ 85°C −−0.1 V
t
w(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted
0°C ≤ Topr ≤ 85°C,
t
w(por1) ≥ 10 s
(2)
−−100 ms
t
w(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
t
w(por1) ≥ 30 s
(2)
−−100 ms
t
w(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
t
w(por1) ≥ 10 s
(2)
−− 1ms
t
w(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted
0°C ≤ Topr ≤ 85°C,
t
w(por1) ≥ 1 s
(2)
−−0.5 ms
NOTES:
1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time.
2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details.
3. V
det1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
V
det1
(3)
Vpor1
Internal reset signal
(“L” valid)
t
w(por1)
tw(Vpor1–Vdet1)
Sampling time
(1, 2)
Vdet1
(3)
1
f
RING-S
× 32
1
f
RING-S
× 32
Vpor2
Vccmin
tw(por2)
tw(Vpor2–Vdet1)
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 30 of 45
REJ03B0144-0140
NOTES:
1. The measurement condition is V
CC = 5.0 V and Topr = 25 °C.
2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock.
3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to
00h.
NOTES:
1. The measurement condition is V
CC = 2.7 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 5.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
− High-speed on-chip oscillator frequency when the
reset is deasserted
V
CC = 5.0 V, Topr = 25 °C − 8 − MHz
− High-speed on-chip oscillator frequency
temperature
• supply voltage dependence
(2)
0 to +60 °C/5 V ± 5 %
(3)
7.76 − 8.24 MHz
-20 to +85 °C/2.7 to 5.5 V
(3)
7.68 − 8.32 MHz
-40 to +85 °C/2.7 to 5.5 V
(3)
7.44 − 8.32 MHz
Table 5.11 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition
Standard
Unit
Min. Typ. Max.
t
d(P-R) Time for internal power supply stabilization during
power-on
(2)
1 − 2000 µs
t
d(R-S)
STOP exit time
(3)
−−150 µs
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 31 of 45
REJ03B0144-0140
NOTES:
1. V
CC = 2.7 to 5.5V, VSS = 0V at Ta = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. 1t
CYC = 1/f1(s)
Table 5.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select
(1)
Symbol Parameter Conditions
Standard
Unit
Min. Typ. Max.
t
SUCYC SSCK clock cycle time 4 −−
t
CYC
(2)
tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC
tLO SSCK clock “L” width 0.4 − 0.6 tSUCYC
tRISE SSCK clock rising time Master −− 1
t
CYC
(2)
Slave −− 1 µs
t
FALL SSCK clock falling time Master −− 1
t
CYC
(2)
Slave −− 1 µs
t
SU SSO, SSI data input setup time 100 −− ns
t
H SSO, SSI data input hold time 1 −−
t
CYC
(2)
tLEAD
SCS setup time
Slave 1t
CYC+50 −− ns
t
LAG
SCS hold time
Slave 1t
CYC+50 −− ns
t
OD SSO, SSI data output delay time −− 1
t
CYC
(2)
tSA SSI slave access time −−1.5tCYC+100 ns
t
OR SSI slave out open time −−1.5tCYC+100 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

R5F211A2DSP#U0

Mfr. #:
Buy R5F211A2DSP#U0
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 8K I-Temp Pb-Free 20-SSOP
Lifecycle:
New from this manufacturer.
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