R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 17 of 45
REJ03B0144-0140
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I
flag is set to 0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/1A Group, R8C/1B Group 3. Memory
Rev.1.40 Dec 08, 2006 Page 18 of 45
REJ03B0144-0140
3. Memory
3.1 R8C/1A Group
Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-
Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
Figure 3.1 Memory Map of R8C/1A Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer•oscillation stop detection•voltage monitor 2
Address break
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM
Expanded area
Internal RAM
SFR
(See 4. Special Function
Registers (SFRs))
0FFFFh
0FFDCh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Part Number
Internal ROM Internal RAM
Size
Address
0YYYYh
R5F211A4SP, R5F211A4DSP, R5F211A4DD, R5F211A4NP,
R5F211A4XXXSP, R5F211A4DXXXSP, R5F211A4XXXDD,
R5F211A4XXXNP
R5F211A3SP, R5F211A3DSP, R5F211A3DD, R5F211A3NP,
R5F211A3XXXSP, R5F211A3DXXXSP, R5F211A3XXXDD,
R5F211A3XXXNP
R5F211A2SP, R5F211A2DSP, R5F211A2DD, R5F211A2NP,
R5F211A2XXXSP, R5F211A2DXXXSP, R5F211A2XXXDD,
R5F211A2XXXNP
R5F211A1SP, R5F211A1DSP, R5F211A1DD,
R5F211A1XXXSP, R5F211A1DXXXSP, R5F211A1XXXDD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
0C000h
0D000h
0E000h
0F000h
1 Kbyte
768 bytes
512 bytes
384 bytes
007FFh
006FFh
005FFh
0057Fh
Size
Address
0XXXXh
R8C/1A Group, R8C/1B Group 3. Memory
Rev.1.40 Dec 08, 2006 Page 19 of 45
REJ03B0144-0140
3.2 R8C/1B Group
Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For
example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
Figure 3.2 Memory Map of R8C/1B Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
Address break
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Expanded area
Internal RAM
SFR
(See 4. Special Function
Registers (SFRs))
0FFFFh
0FFDCh
02BFFh
02400h
Internal ROM
(data Flash)
(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Part Number
Internal ROM Internal RAM
Size
Address
0YYYYh
R5F211B4SP, R5F211B4DSP, R5F211B4DD, R5F211B4NP,
R5F211B4XXXSP, R5F211B4DXXXSP, R5F211B4XXXDD,
R5F211B4XXXNP
R5F211B3SP, R5F211B3DSP, R5F211B3DD, R5F211B3NP,
R5F211B3XXXSP, R5F211B3DXXXSP, R5F211B3XXXDD,
R5F211B3XXXNP
R5F211B2SP, R5F211B2DSP, R5F211B2DD, R5F211B2NP,
R5F211B2XXXSP, R5F211B2DXXXSP, R5F211B2XXXDD,
R5F211B2XXXNP
R5F211B1SP, R5F211B1DSP, R5F211B1DD,
R5F211B1XXXSP, R5F211B1DXXXSP, R5F211B1XXXDD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
0C000h
0D000h
0E000h
0F000h
1 Kbyte
768 bytes
512 bytes
384 bytes
007FFh
006FFh
005FFh
0057Fh
Size
Address
0XXXXh

R5F211A2DSP#U0

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 8K I-Temp Pb-Free 20-SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union