ADRF5130-EVALZ

Data Sheet ADRF5130
Rev. A | Page 9 of 10
Figure 14 shows the ADRF5130 evaluation board with all
components populated. The VDD supply port connects to TP1.
The VDD supply trace has three bypass capacitors 100 pF, 1 µF,
and 1 nF. The TP2 test point connects to the control voltage
port (VCTL). The control trace has a 100 pF bypass capacitor
and 0 Ω resistor. The ground reference connects to GND. A
100 pF dc blocking capacitor is used on all RF traces that connect
the RF1, RF2, and RFC ports to the J1, J2, and J3 connectors,
respectively. The connectors used are 2.9 mm end launch SMA
connectors. Unpopulated capacitor positions are available on all
RF traces to provide extra matching. A through transmission
line (THRU CAL) is available on the ADRF5130 evaluation board
that can measure board loss on the printed circuit board (PCB).
Table 6 shows the bill of materials for the ADRF5130 evaluation
board. The evaluation board shown in Figure 14 is available
from Analog Devices, Inc., upon request.
C4
C6
J3
J2
J1
U1
C5
C7
R1
TP1
TP2
TP3
C1
C2
C3
600-01532-00-2
RF1
RFC
RF2
VDD
GND
VCTL
THRU CAL
12
34
4 3
2
1
43
21
14081-012
Figure 14. ADRF5130-EVALZ Evaluation Board
Table 6. Bill of Materials for the ADRF5130-EVALZ Evaluation Board
Reference Designator Description
J1 to J3 PCB mount SMA connectors
C1 to C4, C7 100 pF capacitors, 0402 package
C5 1 nF capacitor, 0402 package
C6 1 µF capacitor, 0402 package
C8 to C15, C18 to C21 Do not insert (DNI)
R1 0 Ω resistor, 0402 package
TP1, TP2, TP3 Surface-mount test points
U1 ADRF5130 SPDT switch
PCB 600-01532-00-2
1
evaluation PCB; circuit board material: Rogers RO4350 or Arlon 25FR
1
Reference this evaluation board number when ordering the complete evaluation board.
ADRF5130 Data Sheet
Rev. A | Page 10 of 10
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGD-8.
BOTTOM VIEW
TOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.90
0.85
0.80
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
05-25-2016-B
0.30
0.25
0.18
0.20 MIN
2.85
2.70 SQ
2.55
EXPOSED
PAD
PKG-004926/PKG-004866
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 15. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range MSL Rating
2
Package Description Package Option
ADRF5130BCPZ −40°C to +105°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
ADRF5130BCPZ-R7 −40°C to +105°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
ADRF5130-EVALZ −40°C to +105°C Evaluation Board
1
Z = RoHS-Compliant Part.
2
See the Absolute Maximum Ratings section.
©20162017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14081-0-1/17(A)

ADRF5130-EVALZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools Eval Board
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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