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ADRF5130-EVALZ

P1-P3P4-P6P7-P9P10-P11
ADRF5130 Data Sheet
Rev. A | Page 6 of 10
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, ISOLATION, RETURN LOSS, AND IP3
0
–2.5
–2.0
–1.5
–1.0
–0.5
0 1
2 3 4 5
INSERTION LOSS (dB)
FREQUENCY (GHz)
14081-005
RF1
RF2
Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at V
DD
= 5 V
0
–90
–70
–50
–30
–10
–80
–60
–40
–20
ISOLATION (dB)
0 1 2 3
4 5
FREQUENCY (GHz)
14081-006
RF1
RF2
Figure 6. Isolation Between RFC to RF1 or RF2 vs. Frequency at V
DD
= 5 V
–45
0
–35
–25
–15
–5
–40
–30
–20
–10
RETURN LOSS (dB)
0 1 2 3 4 5
FREQUENCY (GHz)
RFC
RF1
RF2
14081-007
Figure 7. Return Loss vs. Frequency at V
DD
= 5 V (RFC, RF1, and RF2)
0
–2.5
–2.0
–1.5
–1.0
–0.5
0 1
2
3 4 5
INSERTION LOSS (dB)
FREQUENCY (GHz)
+105°C
+85°C
+25°C
–40°C
14081-008
Figure 8. Insertion Loss vs. Frequency over Temperature at V
DD
= 5 V
0
–80
–60
–70
–50
–30
–10
–40
–20
ISOLATION (dB)
0 1 2 3 4 5
FREQUENCY (GHz)
14081-009
RF1 ON
RF2 ON
Figure 9. Isolation Between RF1 and RF2 vs. Frequency at V
DD
= 5 V,
Switch Mode On
74
62
0.5 4.0
IP3 (dBm)
FREQUENCY (GHz)
+105°C
+85°C
+25°C
–40°C
64
66
68
70
72
1.0 1.5
2.0 2.5 3.0 3.5
14081-010
Figure 10. IP3 vs. Frequency over Temperature, V
DD
= 5 V
Data Sheet ADRF5130
Rev. A | Page 7 of 10
THEORY OF OPERATION
The ADRF5130 requires a single-supply voltage applied to the
V
DD
pin. Bypass capacitors are recommended on the supply line
to minimize RF coupling.
A digital control voltage applied to the V
CTL
pin controls the
ADRF5130. A small bypassing capacitor is recommended on
these digital signal lines to improve the RF signal isolation.
The ADRF5130 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx pins
are dc-coupled, and dc blocking capacitors are required on the
RF lines. The design is bidirectional; the input and outputs are
interchangeable.
The ideal power-up sequence of the ADRF5130 is as follows:
1. Connect to GND.
2. Power up V
DD
.
3. Power up the digital control input. Powering the digital
control input before the V
DD
supply can inadvertently
forward-bias and damage the ESD protection structures.
4. Power up the RF input. Depending on the logic level
applied to the V
CTL
pin, one RF output port (for example,
RF1) is set to on mode, by which an insertion loss path is
provided from the input to the output, while the other RF
output port (for example, RF2) is set to off mode, by which
the output is isolated from the input.
Table 5. Switch Operation Mode
Digital Control Input (V
CTL
)
Switch Mode
RFC to RF1 RFC to RF2
0 Off mode: the RF1 port is isolated from the RFC
port and is internally terminated to a 50 Ω load to
absorb the applied RF signals.
On mode: a low insertion loss path from the RFC port
to the RF2 port.
1 On mode: a low insertion loss path from the RFC
port to the RF1 port.
Off mode: the RF2 port is isolated from the RFC port
and is internally terminated to a 50 Ω load to absorb
the applied RF signals.
ADRF5130 Data Sheet
Rev. A | Page 8 of 10
APPLICATIONS INFORMATION
Generate the evaluation PCB used in the application circuit
shown in Figure 11 with proper RF circuit design techniques.
Signal lines at the RF port must have a 50 Ω impedance, and the
package ground leads and backside ground slug must connect
directly to the ground plane, as shown in Figure 14.
14081-011
13
GND
GND
RF1
GND
GND
GND GND
14
GND
15
GND
16
RF2
17
GND
18
GND
GND
GND
GND
RFC
GND
19
GND GND
20
GND
21
V
CTL
22
V
DD
23
GND
24
GND
7
8
9
10
11
12
C4
C7
C5
C8
TO C11
C12 TO C15
C6
V
DD
R1
V
CTL
C1
C3
RF1
RF2
RFC
C2
C18 TO C21
1
3
4
2
5
6
Figure 11. Application Circuit
EVALUATION BOARD
The ADRF5130 evaluation board has eight metal layers and
dielectrics between each layer (see Figure 12). The top and the
bottom metal layers have copper thickness of 2 oz (2.7 mil),
whereas the metal layers in between them have 1 oz copper
(1.3 mil) thickness. The top dielectric material is 10 mil Rogers
RO4350, which exhibits a very low thermal coefficient, offering
control over thermal rise of the board. The dielectrics between
other metal layers are FR-4. The overall board thickness
achieved is 62 mil.
Figure 13 shows the top view of the ADRF5130 evaluation
board.
The top copper layer has all RF and dc traces, whereas the other
seven layers provide good ground and help to handle the thermal
rise on the evaluation board caused by the high power of the
ADRF5130. In addition, for proper thermal grounding, many
via holes are provided around the transmission lines and under
the exposed pad of the package. RF transmission lines on the
ADRF5130 evaluation board are coplanar wave guide design with
an 18 mil width and a ground spacing of 13 mil. For controlling
the thermal rise of the ADRF5130 evaluation board at high
temperatures and power levels, it is recommended to use a
heat sink and a mini dc fan.
W = 18mil
G = 13mil
T = 2.7mil
TOTAL THICKNESS = 62mil
H = 10mil
2oz Cu (2.7mil)
RO4350 = 10mil
FR4
FR4
FR4
FR4
FR4
FR4
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
1oz Cu (1.3mil)
2oz Cu (2.7mil)
2oz Cu (2.7mil) 2oz Cu (2.7mil)
14081-013
Figure 12. Evaluation Board Cross-Sectional View
1.500
1.500
0.050
0.050
14081-014
Figure 13. Evaluation Board Top View
P1-P3P4-P6P7-P9P10-P11

ADRF5130-EVALZ

Mfr. #:
Buy ADRF5130-EVALZ
Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools Eval Board
Lifecycle:
New from this manufacturer.
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