LTC3728L-1
25
3728l1fc
APPLICATIONS INFORMATION
Design Example
As a design example for one channel, assume V
IN
=
12V(nominal), V
IN
= 22V(max), V
OUT
= 1.8V, I
MAX
= 5A,
and f = 300kHz.
The inductance value is chosen fi rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
pin to a resistive divider from the INTV
CC
pin, generating
0.7V for 300kHz operation. The minimum inductance for
30% ripple current is:
L
V
IN
–V
OUT
(f)(I
RIPPLE
)
V
OUT
V
IN
or 3.7µH. Using standard inductor values:
I
L
=
V
OUT
(f)(L)
1–
V
OUT
V
IN
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current
will also help ensure that the minimum on-time of 100ns
is not violated. The minimum on-time occurs at maximum
V
IN
:
t
ON(MIN)
=
V
OUT
V
IN(MAX)
f
=
1.8V
22V(300kHz)
= 273ns
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specifi cation with some
accommodation for tolerances:
R
SENSE
60mV
5.84
A
0.01
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pin’s specifi ed
input current.
R1
(MAX)
= 24k
0.8V
2.4V V
OUT
= 24k
0.8V
2.4V 1.8
V
= 32k
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
DS(ON)
= 0.035/0.022, C
MILLER
= 215pF. At
maximum input voltage with T(estimated) = 50°C:
P
MAIN
=
1.8V
22V
5
()
2
1+ (0.005)(50°C–25°C)
[]
0.035
()
+ 22V
()
2
5A
2
4
()
215pF
()
1
5–
2.3
+
1
2.3
300kHz
()
= 332mW
A short-circuit to ground will result in a folded back
current of:
I
SC
=
25mV
0.01
1
2
120ns(22V)
3.3μH
= 2.1A
with a typical value of R
DS(ON)
and δ = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
P
SYNC
=
22V 1.8V
22V
2.1A
()
2
1.125
()
0.022
()
= 100mW
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02 for low output ripple. The
output ripple in continuous mode will be highest at the
LTC3728L-1
26
3728l1fc
APPLICATIONS INFORMATION
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(∆I
L
) = 0.02(1.67A) = 33mV
P–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C
IN
? Do not attempt to split the input decoupling for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the C
IN
capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
3. Do the LTC3728L-1 V
OSENSE
pins’ resistive dividers con-
nect to the (+) terminals of C
OUT
? The resistive divider must
Figure 10. LTC3728L-1 Recommended Printed Circuit Layout Diagram
C
B2
C
B1
R
PU
PGOOD
V
PULL-UP
(<7V)
C
INTVCC
+
C
IN
D1
1µF
CERAMIC
M1 M2
M3
M4
D2
+
C
VIN
V
IN
R
IN
INTV
CC
3.3V
R4R3
R2
R1
RUN/SS1
SENSE1
+
SENSE1
V
OSENSE1
PLLFLTR
PLLIN
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
SENSE2
+
PGOOD
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3728L-1
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
3728L1 F10
+
C
OUT2
+
R
SENSE
R
SENSE
f
IN
F
CERAMIC
LTC3728L-1
27
3728l1fc
APPLICATIONS INFORMATION
be connected between the (+) terminal of C
OUT
and signal
ground. The R2 and R4 connections should not be along
the high current input feeds from the input capacitor(s).
4. Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE
+
and SENSE
should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin con-
nections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between
the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3728L-1 and occupy minimum PC trace area.
Figure 11. Branch Current Waveforms
R
L1
D1
L1
SW1
R
SENSE1
V
OUT1
C
OUT1
+
V
IN
CERAMIC
C
IN
R
IN
+
R
L2
D2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
3728L1 F11
R
SENSE2
V
OUT2
C
OUT2
+
CERAMIC

LTC3728LEGN-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2x, 550kHz, 2-PhSync Reg
Lifecycle:
New from this manufacturer.
Delivery:
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