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MAX11644EUA+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
10 ______________________________________________________________________________________
Detailed Description
The MAX11644/MAX11645 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11644/MAX11645
measure either two single-ended or one differential
input(s). These devices feature a high-speed, 2-wire
serial interface supporting data rates up to 1.7MHz.
Figure 2 shows the simplified internal structure for the
MAX11644/MAX11645.
Power Supply
The MAX11644/MAX11645 operate from a single sup-
ply and consume 670μA (typ) at sampling rates up to
94.4ksps. The MAX11645 feature a 2.048V internal ref-
erence and the MAX11644 feature a 4.096V internal ref-
erence. All devices can be configured for use with an
external reference from 1V to V
DD
.
Analog Input and Track/Hold
The MAX11644/MAX11645 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer
connects C
T/H
between the analog input selected by
CS[0] (see the
Configuration/Setup Bytes (Write Cycle)
section) and GND (Table 3). In differential mode, the
analog-input multiplexer connects C
T/H
to the + and -
analog inputs selected by CS[0] (Table 4).
ANALOG
INPUT
MUX
AIN1
REF
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11644)
2.048V (MAX11645)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H
12-BIT
ADC
V
DD
GND
MAX11644
MAX11645
Figure 2. Simplified Functional Diagram
V
DD
I
OL
I
OH
V
OUT
400pF
SDA
Figure 3. Load Circuit
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 11
During the acquisition interval, the T/H switches are in
the track position and C
T/H
charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
T/H
as a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF x (V
IN+
- V
IN-
) from
C
T/H
to the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog input
to GND. This input capacitor forms an RC filter with the
source impedance limiting the analog-input bandwidth.
For larger source impedances, use a buffer amplifier to
maintain analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte. See the
Slave Address
section.
The T/H circuitry enters hold mode on the falling clock
edge of the acknowledge bit of the address byte (the
ninth clock pulse). A conversion or a series of conver-
sions is then internally clocked and the MAX11644/
MAX11645 hold SCL low. With external clock mode, the
T/H circuitry enters track mode after a valid address on
the rising edge of the clock during the read (R/W = 1)
bit. Hold mode is then entered on the rising edge of the
second clock pulse during the shifting out of the first
byte of the result. The conversion is performed during
the next 12 clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (t
ACQ
) is the minimum time needed for the signal
to be acquired. It is calculated by:
t
ACQ
≥ 95 (R
SOURCE
+ R
IN
) x C
IN
where R
SOURCE
is the analog-input source impedance,
R
IN
= 2.5kΩ, and C
IN
= 22pF. t
ACQ
is 1.5/f
SCL
for internal
clock mode and t
ACQ
= 2/f
SCL
for external clock mode.
Analog Input Bandwidth
The MAX11644/MAX11645 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
TRACK
TRACK
HOLD
C
T/H
C
T/H
TRACK
TRACK
HOLD
AIN0
AIN1
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REF
MAX11644
MAX11645
HOLD
HOLD
TRACK
HOLD
V
DD
/2
Figure 4. Equivalent Input Circuit
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
12 ______________________________________________________________________________________
Analog Input Range and Protection
Internal protection diodes clamp the analog input to V
DD
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (V
DD
+ 0.3V) without causing dam-
age to the device. For accurate conversions, the inputs
must not go more than 50mV below GND or above V
DD
.
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11644/MAX11645 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[0] (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
REF
. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±V
REF
/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the
Transfer Functions
section.
In single-ended mode, the MAX11644/MAX11645
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
REF
.
2-Wire Digital Interface
The MAX11644/MAX11645 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock
line (SCL). SDA and SCL facilitate bidirectional commu-
nication between the MAX11644/MAX11645 and the
master at rates up to 1.7MHz. The MAX11644/
MAX11645 are slaves that transfer and receive data.
The master (typically a microcontroller) initiates data
transfer on the bus and generates the SCL signal to
permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the
Typical
Operating Circuit
). Series resistors (RS) are optional. They
protect the input architecture of the MAX11644/
MAX11645 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11644/MAX11645.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions
section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START (S)
condition, a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
(P) condition, a low-to-high transition on SDA while SCL
is high (Figure 5). A repeated START (Sr) condition
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
HS Mode
section).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11644/MAX11645 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
SCL
SDA
SP
Sr
Figure 5. START and STOP Conditions
SCL
SDA
S
NOT-ACKNOWLEDGE
ACKNOWLEDGE
12 89
Figure 6. Acknowledge Bits
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX11644EUA+

Mfr. #:
Buy MAX11644EUA+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 2Ch 94.4ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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