MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
t
BUF
1.3 μs
Hold Time for START Condition t
HD,STA
0.6 μs
Low Period of the SCL Clock t
LOW
1.3 μs
High Period of the SCL Clock t
HIGH
0.6 μs
Setup Time for a Repeated START
(Sr) Condition
t
SU,STA
0.6 μs
Data Hold Time t
HD,DAT
(Note 11) 0 900 ns
Data Setup Time t
SU,DAT
100 ns
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
Measured from 0.3V
DD
- 0.7V
DD
20 + 0.1C
B
300 ns
Fall Time of SDA Transmitting t
F
Measured from 0.3V
DD
- 0.7V
DD
(Note 12) 20 + 0.1C
B
300 ns
Setup Time for STOP Condition t
SU,STO
0.6 μs
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
Serial-Clock Frequency f
SCLH
(Note 14) 1.7 MHz
Hold Time, Repeated START
Condition
t
HD,STA
160 ns
Low Period of the SCL Clock t
LOW
320 ns
High Period of the SCL Clock t
HIGH
120 ns
Setup Time for a Repeated START
Condition
t
SU
,
STA
160 ns
Data Hold Time t
HD
,
DAT
(Note 11) 0 150 ns
Data Setup Time t
SU
,
DAT
10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
20 80 ns
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
- 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
- 0.7V
DD
(Note 12) 20 160 ns
Setup Time for STOP Condition t
SU
,
STO
160 ns
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
(Notes 11 and 14) 0 10 ns
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11645), V
DD
= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11644 is tested at V
DD
= 5V and the MAX11645 is tested at V
DD
= 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1μF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300μV
P-P
.
Note 10: Measured for the MAX11645 as:
and for the MAX11644, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
VVVV
V
V
FS FS
N
REF
(. ) (. )
(.
55 45
2
55
×
45.)V
VVVV
V
V
FS FS
N
REF
(. ) (. )
(.
36 27
2
36
×
27.)V
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
6 _______________________________________________________________________________________
Typical Operating Characteristics
(V
DD
= 3.3V (MAX11645), V
DD
= 5V (MAX11644), f
SCL
= 1.7MHz, 50% duty cycle, f
SAMPLE
= 94.4ksps, single-ended, unipolar,
T
A
= +25°C, unless otherwise noted.)
-0.5
-0.2
-0.4
-0.3
0.2
0.1
-0.1
0
0.3
0.5
0 4000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11644 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
1000 1500500
2000 2500
3000 3500
0.4
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11644 toc02
DIGITAL OUTPUT CODE
INL (LSB)
0 4000
1000 1500500
2000 2500
3000 3500
-140
-120
-100
-80
-60
-40
-20
0 10k 20k 30k 40k 50k
FFT PLOT
MAX11644 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
f
SAMPLE
= 94.4ksps
f
IN
= 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX11644 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
INTERNAL REFERENCE MAX11644
INTERNAL REFERENCE MAX11645
EXTERNAL REFERENCE MAX11644
EXTERNAL REFERENCE MAX11645
0
0.2
0.1
0.4
0.3
0.5
0.6
2
.75
.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11644 toc05
SUPPLY VOLTAGE (V)
I
DD
(μA)
3.73.24.24.7
SDA = SCL = V
DD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5
-25
20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11644 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX11644
MAX11645
0
200
100
300
400
500
600
700
800
900
1000
0 20406080100
ANALOG SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
MAX11644 toc07
CONVERSION RATE (ksps)
AVERAGE I
DD
(μA)
0
EXTERNAL REFERENCE
INTERNAL REFERENCE ALWAYS ON

MAX11644EUA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 2Ch 94.4ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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