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MAX11644EUA+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 13
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11644/MAX11645
continuously wait for a START condition followed by
their slave address. When the MAX11644/MAX11645
recognize their slave address, they are ready to accept
or send data. The slave address is factory programmed
to 0110110. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX11644/MAX11645
(R/W = 0 selects a write condition, R/W = 1 selects a
read condition). After receiving the address, the
MAX11644/MAX11645 (slave) issues an acknowledge
by pulling SDA low for one clock cycle.
Bus Timing
At power-up, the MAX11644/MAX11645 bus timing is
set for fast-mode (F/S mode), which allows conversion
rates up to 22.2ksps. The MAX11644/MAX11645 must
operate in high-speed mode (HS mode) to achieve con-
version rates up to 94.4ksps. Figure 1 shows the bus
timing for the MAX11644/MAX11645’s 2-wire interface.
HS Mode
At power-up, the MAX11644/MAX11645 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After suc-
cessfully receiving the HS-mode master code, the
MAX11644/MAX11645 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle (Figure
8). After the not-acknowledge, the MAX11644/
MAX11645 are in HS mode. The bus master must then
send a repeated START followed by a slave address to
initiate HS mode communication. If the master gener-
ates a STOP condition, the MAX11644/MAX11645
return to F/S mode.
011 10 1 0 R/W A
SLAVE ADDRESS
S
SCL
SDA
123456789
MAX11644/MAX11645
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
Figure 7. MAX11644/MAX11645 Slave Address Byte
000 10XXXA
HS-MODE MASTER CODE
SCL
SDA
S Sr
F/S MODE HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
14 ______________________________________________________________________________________
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by seven address bits
(Figure 7) and a write bit (R/W = 0). If the address byte
is successfully received, the MAX11644/MAX11645
(slave) issues an acknowledge. The master then writes
to the slave. The slave recognizes the received byte as
the set-up byte (Table 1) if the most significant bit
(MSB) is 1. If the MSB is 0, the slave recognizes that
byte as the configuration byte (Table 2). The master
can write either one or two bytes to the slave in any
order (setup byte, then configuration byte; configura-
tion byte, then setup byte; setup byte or configuration
byte only; Figure 9). If the slave receives a byte suc-
cessfully, it issues an acknowledge. The master ends
the write cycle by issuing a STOP condition or a repeat-
ed START condition. When operating in HS mode, a
STOP condition returns the bus into F/S mode (see the
HS Mode
section).
Figure 9. Write Cycle
BIT 7
(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
(LSB)
REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X
BIT NAME DESCRIPTION
7 REG Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage (Table 6).
Default to 000 at power-up.
3 CLK 1 = external clock, 0 = internal clock. Defaults to 0 at power-up.
2 BIP/UNI 1 = bipolar, 0 = unipolar. Defaults to 0 at power-up (see the Unipolar/Bipolar section).
1 RST 1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
0 X Don’t-care bit. This bit can be set to 1 or 0.
Table 1. Setup Byte Format
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________ 15
BIT 7
(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
(LSB)
REG SCAN1 SCAN0 X X X CS0 SGL/DIF
BIT NAME DESCRIPTION
7 REG Register bit. 1 = setup byte (see Table 1), 0 = configuration byte.
6 SCAN1
5 SCAN0
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.
4X
3X
2X
1 CS0
Channel select bit. CS0 selects which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up.
0 SGL/DIF
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-
Ended/Differential Input section.
Table 2. Configuration Byte Format
CS0 AIN0 AIN1 GND
0+ -
1+-
X = Don’t care.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS0 AIN0 AIN1
0+ -
1-+
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX11644EUA+

Mfr. #:
Buy MAX11644EUA+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 2Ch 94.4ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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