1©2016 Integrated Device Technology, Inc Revision B March 3, 2016
General Description
The 810001-21 is a PLL based synchronous clock generator that is
optimized for digital video clock jitter attenuation and frequency
translation. The device contains two internal frequency multiplication
stages that are cascaded in series. The first stage is a VCXO PLL
that is optimized to provide reference clock jitter attenuation, and to
support the complex PLL multiplication ratios needed for video rate
conversion. The second stage is a FemtoClock™ frequency
multiplier that provides the low jitter, high frequency video output
clock.
Preset multiplication ratios are selected from internal lookup tables
using device input selection pins. The multiplication ratios are
optimized to support most common video rates used in professional
video system applications. The VCXO requires the use of an
external, inexpensive pullable crystal. Two crystal connections are
provided (pin selectable) so that both 60 and 59.94 base frame rates
can be supported. The VCXO requires external passive loop filter
components which are used to set the PLL loop bandwidth and
damping characteristics.
Features
Jitter attenuation and frequency translation of video clock signals
Supports SMPTE 292M, ITU-R Rec. 601/656 and
MPEG-transport clocks
Support of High-Definition (HD) and Standard-Definition (SD)
pixel rates
Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates
in one device
Supports both 1000/1001 and 1001/1000 rate conversions
Dual PLL mode for high-frequency clock generation (36MHz to
148.5MHz)
VCXO-PLL mode for low-frequency clock generation (27MHz and
26.973MHz)
One LVCMOS/LVTTL clock output
Two selectable LVCMOS/LVTTL clock inputs
LVCMOS/LVTTL compatible control signals
RMS phase jitter @148.3516MHz, (12kHz - 20MHz):
1.089ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Supported Input Frequencies Supported Output Frequencies
f
VCXO
= 27MHz f
VCXO
= 26.973MHz
27.0000MHz 26.9730MHz
27.0270MHz 27.0000MHz
74.1758MHz 74.1016MHz
74.3243MHz 74.2499MHz
74.2500MHz 74.1758MHz
27.0270MHz 27.0000MHz
26.9730MHz 26.9461MHz
74.1758MHz 74.1016kHz
45.0000kHz 44.9550kHz
33.7500kHz 33.7163kHz
15.6250kHz 15.6094kHz
15.7343kHz 15.7185kHz
28.1250kHz 28.0969kHz
f
VCXO
= 27MHz f
VCXO
= 26.973MHz
148.5000MHz 148.3515MHz
74.2500MHz 74.1758MHz
49.5000MHz 49.4505MHz
33.0000MHz 32.9670MHz
162.0000MHz 161.8380MHz
81.0000MHz 80.9190MHz
54.0000MHz 53.9460MHz
36.0000MHz 35.9640MHz
27.0000MHz 26.9730MHz
810001-21
Data Sheet
FemtoClock™ Dual VCXO Video PLL
2©2016 Integrated Device Technology, Inc Revision B March 3, 2016
810001-21 Data Sheet
Block Diagram
Pin Assignment
Charge
Pump
VCXO
V3:V0
Phase
Detector
Q
Output
Divider
00 = 4
(default)
01 = 8
10 = 12
11 = 18
VCXO Feedback Divider
(M Value from Table)
VCXO Input
Pre-Divider
(P Value
from Table)
VCXO Jitter Attenuation PLL
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
LF1
LF0
ISET
Loop
Filter
VCXO
Divider
Table
OE
XTAL_SEL
01
MF
MR
Master Reset
0
1
CLK0
CLK1
CLK_SEL
N1:N0
4
2
11
10
10
11
01
01
10
11
00
2
nBP1:nBP0
FemtoClock
Frequency Multiplier
0= x22 (default)
1= x24
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LF1
LF0
ISET
V
DD
nBP0
GND
CLK_SEL
CLK1
N0
N1
nBP1
OE
GND
Q
V
DDO
V
DDA
CLK0
V0
V
DD
MR
MF
V1
V2
V3
XTAL_IN0
XTAL_OUT0
GND
XTAL_IN1
XTAL_OUT1
XTAL_SEL
V
DD
VDDX
810001-21
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
3©2016 Integrated Device Technology, Inc Revision B March 3, 2016
810001-21 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 LF1, LF0
Analog
Input/Output
Loop filter connection node pins.
3 ISET
Analog
Input/Output
Charge pump current setting pin.
4, 11, 25 V
DD
Power Core supply pins.
5, 22
nBP0,
nBP1
Input Pullup PLL Bypass control pins. See block diagram.
6, 20, 29 GND Power Power supply ground.
7 CLK_SEL Input Pulldown
Input clock select. When HIGH selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
8, 9 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
10, 14,
15, 16
V0, V1,
V2, V3
Input Pulldown VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
12 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the output to go low. When logic LOW, the internal dividers and the
output is enabled. LVCMOS/LVTTL interface levels.
13 MF Input Pulldown FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels.
17 V
DDA
Power Analog supply pin.
18 V
DDO
Power Output supply pin.
19 Q Output Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels.
21 OE Input Pullup
Output enable. When logic LOW, the clock output is in high-impedance. When
logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels.
23, 24 N1, N0 Input Pulldown FemtoClock output divide select pins. LVCMOS/LVTTL interface levels.
26 XTAL_SEL Input Pulldown
Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0.
LVCMOS/LVTTL interface levels.
27,
28
XTAL_OUT1,
XTAL_IN1
Input Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output.
30,
31
XTAL_OUT0,
XTAL_IN0
Input Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output.
32 V
DDX
Power Power supply pin for VCXO charge pump.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
(per output)
V
DD
= V
DDO
= 3.465V 8.5 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance 22.5

810001DK-21LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVCMOS OUT VCXO FEMTOCLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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