13©2016 Integrated Device Technology, Inc Revision B March 3, 2016
810001-21 Data Sheet
Schematic Example
Figure 3 shows an example of the 810001-21 application schematic.
In this example, the device is operated at V
DD
= V
DDX
= V
DDO
=
V
DDA
= 3.3V. The decoupling capacitors should be located as close
as possible to the power pin. The input is driven by a 3.3V 17
LVCMOS driver. An optional 3-pole filter can also be used for
additional spur reduction. It is recommended that the loop filter
components be laid out for the 3-pole option. This will also allow the
2-pole filter to be used. For the LVCMOS output, a termination
example is shown in this schematic. For more termination
approaches, please refer to the LVCMOS Termination Application
Note.
Figure 3. 810001-21 Schematic Example
U1
810001-21 Schematic
LF1
1
LF0
2
ISET
3
VDD
4
nBP0
5
GND
6
CLK_SEL
7
CLK1
8
CLK0
9
V0
10
VDD
11
MR
12
MF
13
V1
14
V2
15
V3
16
VDDA
17
VDDO
18
Q
19
GND
20
OE
21
nBP1
22
N1
23
N0
24
32
VDDX
31
XTAL_IN0
30
XTAL_OUT0
29
GND
28
XTAL_IN1
27
XTAL_OUT1
26
XTAL_SEL
VDD
25
12pF
12pF
C8
.01uF
X1
VDD
Set Logic
Input to '0'
To Logic
Input
pins
Logic Control Input Examples
To Logic
Input
pins
Set Logic
Input to '1'
RU2
Not Install
RU1
1K
RD2
1K
RD1
Not Install
VDDVDD
MR Control
VDDA
X2
Pin25
R6
TBD
Cp2
TBD
Cp1
TBD
Rs1
TBD
Cs1
TBD
LF1
3-pole loop filter example -
(optional)
LF0
VDD
Q1
Driver_LVCMOS
Q2
Driver_LVCMOS
Rs
150K
R1
33
R2
33
Pin18
Pin11Pin4
Rset
2.21K
TL2
Zo = 50
TL1
Zo = 50
C5
.01uF
VDD
2-pole loop filter
C10
.01uF
C9
10uF
R3
10
VDD
C1spare
C2spare
C3 spare
C4 spare
Cs
.22uF
Cp
.001uF
C6
.01uF
VDDX
C12
.01uF
C11
10uF
R4
10
C7
.01uF
VDD
VDDX
VDD
VDDA
VDD
R5
33
TL3
Zo = 50
Receiver
14©2016 Integrated Device Technology, Inc Revision B March 3, 2016
810001-21 Data Sheet
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must be
taken with the package and load capacitance (C
L
). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application Note.
The crystal’s load capacitance C
L
characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (C
TUNE
).
If the crystal C
L
is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal C
L
is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of C
L
is dependent on the characteristics
of the VCXO. The recommended C
L
in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
The frequency of oscillation in the
third overtone mode is not
necessarily at exactly three times
the fundamental frequency. The
mechanical properties of the
quartz element dictate the
position of the overtones relative
to the fundamental. The oscillator
circuit may excite both the
fundamental and overtone modes
simultaneously. This will cause a
nonlinearity in the tuning curve.
This potential problem is why VCXO crystals are required to be
tested for absence of any activity inside a ±200ppm window at three
times the fundamental frequency. Refer to F
L_3OVT
and
F
L_3OVT_spurs
in the crystal Characteristics table.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
should be kept separate and not run underneath the device, loop
filter or crystal components.
VCXO Characteristics Table
VCXO-PLL Loop Bandwidth Selection Table
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
R
S
C
S
C
P
R
SET
C
TUNE
C
TUNE
19.44MHz
Symbol Parameter Typical Units
k
VCXO
VCXO Gain 6.6 kHz/V
C
V_LOW
Low Varactor Capacitance 15 pF
C
V_HIGH
High Varactor Capacitance 29 pF
Bandwidth Crystal Frequency (MHz) M R
S
(k)C
S
(µF) C
P
(µF) R
SET
(k)
6Hz (Low) 27 4004 175 4.7 0.01 8.0
80Hz (Mid) 27 1000 150 0.22 0.001 2.21
475Hz (High) 27 92 125 0.1 0.0001 3.3
15©2016 Integrated Device Technology, Inc Revision B March 3, 2016
810001-21 Data Sheet
Crystal Characteristics
Reliability Information
Table 6.
JA
vs. Air Flow Table for a 32 Lead VFQFN
Transistor Count
The transistor count for 810001-21 is: 9365
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
f
N
Frequency
27 MHz
26.973 MHz
f
T
Frequency Tolerance ±20 ppm
f
S
Frequency Stability ±20 ppm
Operating Temperature Range 0 70
0
C
C
L
Load Capacitance 12 pF
C
O
Shunt Capacitance 4 pF
C
O
/ C
1
Pullability Ratio 220 240
F
L_3OVT
3
RD
Overtone F
L
200 ppm
F
L_3OVT_spurs
3
RD
Overtone F
L
Spurs 200 ppm
ESR Equivalent Series Resistance 20
Drive Level 1mW
Aging @ 25
0
C ±3 per year ppm
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W

810001DK-21LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVCMOS OUT VCXO FEMTOCLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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