Obsolete Product(s) - Obsolete Product(s)
Functional description STLC7550
10/24 Rev 9
Figure 3. Clock Block Diagram
2.4 Modes of operation
Thanks to MCM and M/S programmation pins we can get the following configuration.
Configuration 1 : MCM = 1, M/S
= 1
The STLC7550 is in master mode and we have :
Fs = XTAL IN / (M x Q x OVER)
Fs and SCLK are output pins.
Figure 4. Configuration 1
Configuration 2 : MCM = 1, M/S
= 0
The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor
generates the Fs and controls the phase of the sampling frequency.
Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER).
Configuration 3 : MCM = 0, M/S
= 1
The STLC7550 is in master mode and the processor provides the XTAL IN = MCLK =
OCLK. The STLC7550 generates the Fs from OCLK. In this mode the configuration 3 is
equivalent to the STLC7546 mode.
Configuration 4 : MCM = 0, M/S
= 0
The STLC7550 is in slave mode. The configuration 4 is equivalent to configuration 3 but the
Fs is generated and phase controlled by the processor.
Bit 3-4-5
Internal
Sampling
M/S
Sync
FS
SCLK
(OCLK)
% OVER
XTALIN
(MCLK)
XTALOUT
÷ M ÷ Q
MCM
Cont. Reg. : Bit 8-9-10-11-12-13
V
DD
SCLK
FS
DIN
DOUT
BCLK
FS
DO
DI
XTALIN
M/S
MCM
STLC7550
PROCESSOR
V
DD
f
Q
= 36.864MHz
V
DD
TS GND
