E-STLC7550TQF7 Datasheet E-STLC7550TQF7, STLC7550TQF7 | P4-P6

Obsolete Product(s) - Obsolete Product(s)

Pins description & Block diagram STLC7550

4/24 Rev 9

Note: 1 To obtain published performance, the analog V

and Digital V

should be decoupled with

respect to Analog Ground and Digital Ground, respectively. The decoupling is intended to

isolate digital noise from the analog section ; decoupling capacitors should be as close as

possible to the respective analog and digital supply pins.

2 All the ground pins must be tied together. In the following section, the ground and supply

pins are referred to as GND and V

, respectively.

1.1 Pin description

1.1.1 Power Supply (5 pins)

Analog V

Supply (AV

)

This pin is the positive analog power supply voltage for the DAC and the ADC section.

It is not internally connected to digital V

supply (DV

In any case the voltage on this pin must be higher or equal to the voltage of the Digital power

supply (DV

Digital VDD Supply (DVDD)

This pin is the positive digital power supply for DAC and ADC digital internal circuitry.

Analog Ground (AGND1, AGND2)

These pins are the ground return of the analog DAC (ADC) section.

21 AGND1 I Analog Ground

27 AUXIN+ I Non-inverting Input to Auxiliary Analog Input

28 AUXIN- I Inverting Input to Auxiliary Analog Input

29 IN+ I Non-inverting Input to Analog Input Amplifier

30 IN- I Inverting Input to Analog Input Amplifier

31 AV

I Positive Analog Power Supply (2.7V to 5.5V)

32 V

O Common Mode Voltage Output (AVDD/2)

33 AGND2 I Analog Ground

39 OUT+ O Non-inverting Smoothing Filter Output

40 OUT- O Inverting Smoothing Filter Output

41 RESET

I Reset Function to initialize the internal counters

42 TS I Timeslot Control Input

43 TSTD1 I/O Digital Input/Output reserved for test

44 DIN I Serial Data Input

45 DOUT O Serial Data Output

Table 1. Pin list (continued)

Pin # Pin Name Type Description

Obsolete Product(s) - Obsolete Product(s)

STLC7550 Pins description & Block diagram

Rev 9 5/24

Digital Ground (DGND)

This pin is the ground for DAC and ADC internal digital circuitry.

1.1.2 Host interface (10 pins)

Data In (DIN)

In Data Mode, the data word is the input of the DAC channel. In software, the data word is

followed by the control register word.

Data Out (DOUT)

In Data Mode, the data word is the ADC conversion result. In software, the data word is

followed by the register read.

Frame Synchronization (FS)

In master mode, the frame synchronization signal is used to indicate that the device is ready

to send and receive data. The data transfer begins on the falling edge of the frame-sync

signal. The framesync is generated internally and goes low on the rising edge of SCLK in

master mode. In slave mode the frame is generated externally.

Serial Bit Clock (SCLK)

SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization

interval. The Serial bit clock is generated internally.

Reset Function (RESET)

The reset function is to initialize the internal counters and control register. A minimum low

pulse of 100ns is required to reset the chip. This reset function initiates the serial data

communications. The reset function will initialize all the registers to their default value and

will put the device in a pre-programmed state. After a low-going pulse on RESET

, the device

registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface

will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to

0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor

will be set on the main inputs IN+ and IN-. After a reset condition, the first frame

synchronization corresponds to the primary channel.

Power Down (PWRDWN)

The Power-Down input powers down the entire chip (< 50mW). When PWRDWN Pin is

taken low, the device powers down such that the existing internally programmed state is

maintained. When PWRDWN

is driven high, full operation resumes after 1ms. If the

PWRDWN

input is not used, it should be tied to V

Hardware Control (HC0, HC1)

These two pins are used for Hardware/Software Control of the device. The data on HC0 and

HC1 will be latched on to the device on the rising edge of the Frame Synchronization Pulse.

If these two pins are low, Software Control Mode is selected. When in Software Control

Mode, the LSB of the 16-bit word will select the Data Mode (LSB = 0) or the Control Mode

(LSB = 1). Other combinations of HC0/HC1 are for Hardware Control. These inputs should

be tied low if not used.

Obsolete Product(s) - Obsolete Product(s)

Pins description & Block diagram STLC7550

6/24 Rev 9

Master/Slave Control (M/S)

When M/S is high, the device is in master mode and Fs is generated internally. When M/S is

low, the device is in slave mode and Fs must be generated externally.

Master Clock Mode (MCM)

When MCM is high, XTALIN is provided externally and must be equal to 36.864MHz. When

MCM is low, XTALIN is provided externally and must be equal to oversampling frequency :

Fs x Over (see Figure 3 and Section 2.4).

Timeslot Control (TS)

When TS = 0 the data are assigned to the first 16 bits after falling edge of FS (7546 mode)

otherwise the data are bits 17 to 32. The case M/S

= 1 with TS = 1 is reserved for life-test

(transmit gain fixed to 0dB).

1.1.3 Clock signals (2 pins)

Depending on MCM value, these pins have different function.

MCM = 1 (XTALIN, XTALOUT)

These pins must be tied to external crystal. For the value of crystal see Section 2.3.

MCM = 0 (MCLK, XTALOUT)

MCLK Pin must be connected to an external clock. XTALOUT is not used.

1.1.4 Analog interface (9 pins)

DAC and ADC Positive Reference Voltage Output (V

REFP

)

This pin provides the Positive Reference Voltage used by the 16-bit converters. The

reference voltage, V

REF

, is the voltage difference between the V

REFP

and V

REFN

outputs,

and its nominal value is 1.25V. V

REFP

should be externally decoupled with respect to V

DAC and ADC Negative Reference Voltage Output (V

REFN

)

This pin provides the Negative Reference Voltage used by the 16-bit converters, and should

be externally decoupled with respect to V

Common Mode Voltage Output (V

)

This output pin is the common mode voltage (AV

- AGND)/2. This output must be

decoupled with respect to GND.

Non-inverting Smoothing Filter Output(OUT+)

This pin is the non-inverting output of the fully differential analog smoothing filter.

Inverting Smoothing Filter Output (OUT-)

This pin is the inverting output of the fully differential analog smoothing filter. Outputs OUT+

and OUTprovide analog signals with maximum peak-topeak amplitude 2 x VREF, and must

be followed by an external two pole smoothing filter. The external filter follows the internal

single pole switch capacitor filter. The cutoff frequency of the external filter must be greater

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E-STLC7550TQF7

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IC AFE 1 CHAN 16BIT 48TQFP

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