Obsolete Product(s) - Obsolete Product(s)
STLC7550 Functional description
Rev 9 13/24
Figure 9. Data Mode
Figure 10. Mixed Mode
2.6 Control register
This section defines the control and device status information. The register programming
occurs only during Secondary Frame Synchronization. After a reset condition, the device is
always in data mode.
0 1 X 16bits No Hardware Mode for Data Transfer only.
1 X X 16bits (+16bits reg.) Yes
Hardware Mode for Data Transfer +
Control Register Transfer.
Table 3. Mode selection (continued)
HC1 HC0 LSB Useful Data
Secondary
FSYNC
Description
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
D15 D14--
--
FS
SCLK
TxDI
HC1, HC0
Sampling period
00 or 01
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
D15 D14--
--
TxDO
Sampling Period
1/2 Sampling Period (see Note)
FS
TxDI
HC1, HC0
1X
Data Word Input Control Word
01
SCLK
TxDO
Data Word Output Register Word
Note :
In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.
Table 4. Bits Assignment
Bits Name Function Reset Value
0 - - 0
1 D1 Aux/Main Input 0
2 D2 Receive Gain 0
Obsolete Product(s) - Obsolete Product(s)
Functional description STLC7550
14/24 Rev 9
Note: 1 Not recommended case. Performances could be reduced.
3 D3 Oversampling bit 0 0
4 D4 Oversampling bit 1 0
5 D5 Oversampling bit 2 0
6 D6 Attenuator transmit bit 0 0
7 D7 Attenuator transmit bit1 0
8 M M Divider 1
9 Q0 Q0 Divider 1
10 Q1 Q1 Divider 0
11 Q2 Q2 Divider 0
12 T0 M Divider and Test mode bit 0 0
13 T1 M Divider and Test mode bit 1 0
14 TEST2 Test mode bit 2 0
15 TEST3 Test mode bit 3 0
Table 5. Aux/Main Input
D1 Function
0 Main Receive Input
1 Auxiliary Receive Input
Table 6. Receive Gain
D2 Function
DIFFERENTIAL INPUT
0 0dB gain (commun mode fixed)
1 +6dB gain (commun mode non-fixed)
SINGLE ENDED (one input used, other at V
CM
)
0 -6dB gain (see Note 1)
1 0dB gain
Table 4. Bits Assignment (continued)
Bits Name Function Reset Value
Table 7. Oversampling Ratio
D5 D4 D3 Function
0 0 0 160
0 0 1 192
0 1 0 Reserved
0 1 1 Reserved
Obsolete Product(s) - Obsolete Product(s)
STLC7550 Functional description
Rev 9 15/24
This two bits must be set to 0 for normal operation.
1 0 0 Reserved
1 0 1 64
1 1 0 96
1 1 1 128
Table 8. Transmit Attenuation
D7 D6 Function
0 0 Infinite
0 1 Reserved
1 0 -6dB
1 1 0dB
Table 9. Q Divider Clock Generator
D11 D10 D9 Function
0 0 0 Q divider = 5
0 0 1 Q divider = 6
0 1 0 Q divider = 7
0 1 1 Q divider = 8
1 0 0 Q divider = 4.5
1 0 1 Q divider = 5.5
1 1 0 Q divider = 6.5
1 1 1 Q divider = 7.5
Table 10. M Divider Clock Generator
D13 D12 D8 Function
0 0 0 M divider = 3
0 0 1 M divider = 4
0 1 X Reserved
1 0 X Reserved
1 1 0 M divider = 1
1 1 1 M divider = 2
Table 11. Reserved Mode
D15 D14 Function
X X Reserved for test
Table 7. Oversampling Ratio (continued)
D5 D4 D3 Function

E-STLC7550TQF7

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC AFE 1 CHAN 16BIT 48TQFP
Lifecycle:
New from this manufacturer.
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